Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs
Identifieur interne : 002C91 ( Main/Repository ); précédent : 002C90; suivant : 002C92Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs
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Abstract
Drain bias stress effects on amorphous Zinc Indium Oxide (a-ZIO) Thin Film Transistors (TFTs) are important in flexible electronic systems. The drain bias impacts the overall threshold voltage (Vth) shift more so in the saturation stress mode than in the linear stress mode. Localization of degradation region in channel results in asymmetry in post stressed drain current in forward and reverse operations. This brief studies the impact of drain bias on Vth degradation, and also the effect on post stressed forward and reverse currents in a-ZIO TFTs, under both positive and negative gate bias stress in different regions of operation. Based on the measured results, an empirical expression incorporating drain bias effect on Vth degradation is derived. Also the measured results point to charge trapping in the insulator-semiconductor interface as the dominant degradation mechanism.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs</title><author><name sortKey="Dey, Aritra" uniqKey="Dey A">Aritra Dey</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>School of Electrical, Computing and Energy Engineering, Arizona State University</s1><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>School of Electrical, Computing and Energy Engineering, Arizona State University</wicri:noRegion></affiliation></author><author><name sortKey="Allee, David R" uniqKey="Allee D">David R. Allee</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>School of Electrical, Computing and Energy Engineering, Arizona State University</s1><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>School of Electrical, Computing and Energy Engineering, Arizona State University</wicri:noRegion></affiliation></author><author><name sortKey="Clark, Lawrence T" uniqKey="Clark L">Lawrence T. Clark</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>School of Electrical, Computing and Energy Engineering, Arizona State University</s1><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>School of Electrical, Computing and Energy Engineering, Arizona State University</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">11-0297577</idno><date when="2011">2011</date><idno type="stanalyst">PASCAL 11-0297577 INIST</idno><idno type="RBID">Pascal:11-0297577</idno><idno type="wicri:Area/Main/Corpus">002F63</idno><idno type="wicri:Area/Main/Repository">002C91</idno></publicationStmt><seriesStmt><idno type="ISSN">0038-1101</idno><title level="j" type="abbreviated">Solid-state electron.</title><title level="j" type="main">Solid-state electronics</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Amorphous material</term><term>Charge carrier trapping</term><term>Damaging</term><term>Dielectric materials</term><term>Drain</term><term>Drain current</term><term>Electric stress</term><term>Electronic component</term><term>Flexible structure</term><term>Indium oxide</term><term>Insulator</term><term>Stress effects</term><term>Thin film transistor</term><term>Voltage threshold</term><term>Zinc oxide</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Drain</term><term>Contrainte électrique</term><term>Transistor couche mince</term><term>Effet contrainte</term><term>Composant électronique</term><term>Seuil tension</term><term>Endommagement</term><term>Courant drain</term><term>Piégeage porteur charge</term><term>Isolateur</term><term>Matériau amorphe</term><term>Oxyde de zinc</term><term>Oxyde d'indium</term><term>Structure flexible</term><term>Diélectrique</term><term>ZnO</term></keywords><keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Composant électronique</term><term>Matériau amorphe</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Drain bias stress effects on amorphous Zinc Indium Oxide (a-ZIO) Thin Film Transistors (TFTs) are important in flexible electronic systems. The drain bias impacts the overall threshold voltage (V<sub>th</sub>) shift more so in the saturation stress mode than in the linear stress mode. Localization of degradation region in channel results in asymmetry in post stressed drain current in forward and reverse operations. This brief studies the impact of drain bias on V<sub>th</sub> degradation, and also the effect on post stressed forward and reverse currents in a-ZIO TFTs, under both positive and negative gate bias stress in different regions of operation. Based on the measured results, an empirical expression incorporating drain bias effect on V<sub>th</sub> degradation is derived. Also the measured results point to charge trapping in the insulator-semiconductor interface as the dominant degradation mechanism.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0038-1101</s0></fA01><fA03 i2="1"><s0>Solid-state electron.</s0></fA03><fA05><s2>62</s2></fA05><fA06><s2>1</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs</s1></fA08><fA11 i1="01" i2="1"><s1>DEY (Aritra)</s1></fA11><fA11 i1="02" i2="1"><s1>ALLEE (David R.)</s1></fA11><fA11 i1="03" i2="1"><s1>CLARK (Lawrence T.)</s1></fA11><fA14 i1="01"><s1>School of Electrical, Computing and Energy Engineering, Arizona State University</s1><s3>USA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ></fA14><fA20><s1>19-24</s1></fA20><fA21><s1>2011</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>2888</s2><s5>354000189906560040</s5></fA43><fA44><s0>0000</s0><s1>© 2011 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>26 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>11-0297577</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>Solid-state electronics</s0></fA64><fA66 i1="01"><s0>GBR</s0></fA66><fC01 i1="01" l="ENG"><s0>Drain bias stress effects on amorphous Zinc Indium Oxide (a-ZIO) Thin Film Transistors (TFTs) are important in flexible electronic systems. The drain bias impacts the overall threshold voltage (V<sub>th</sub>) shift more so in the saturation stress mode than in the linear stress mode. Localization of degradation region in channel results in asymmetry in post stressed drain current in forward and reverse operations. This brief studies the impact of drain bias on V<sub>th</sub> degradation, and also the effect on post stressed forward and reverse currents in a-ZIO TFTs, under both positive and negative gate bias stress in different regions of operation. Based on the measured results, an empirical expression incorporating drain bias effect on V<sub>th</sub> degradation is derived. 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