A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets
Identifieur interne : 002101 ( Main/Repository ); précédent : 002100; suivant : 002102A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets
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Abstract
We report a three-mask-processed coplanar amorphous-InGaZnO thin-film transistor (TFT) with equal offsets at the source and drain sides. TFTs with offset lengths ranging from 1.5 to 4.0 μm exhibit good switching characteristics with turn-on voltage around -1.6 V, gate swing of ˜0.1 V/decade, and on/off current ratio > 105. While gate swing and turn-on voltage are independent of the offset length, the field-effect mobility decreases from 2.4 to 0.5 cm2/V.s as the offset length increases from 1.5 to 4 μm. This coplanar TFT is suitable for cost-effective active-matrix displays with minimal kickback/feedthrough voltage.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets</title><author><name>UNG GI LEE</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Advanced Display Research Center, Department of Information Display, Kyung Hee University</s1><s2>Seoul 130-701</s2><s3>KOR</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Corée du Sud</country><placeName><settlement type="city">Séoul</settlement></placeName></affiliation></author><author><name sortKey="Mativenga, Mallory" uniqKey="Mativenga M">Mallory Mativenga</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Advanced Display Research Center, Department of Information Display, Kyung Hee University</s1><s2>Seoul 130-701</s2><s3>KOR</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Corée du Sud</country><placeName><settlement type="city">Séoul</settlement></placeName></affiliation></author><author><name>DONG HAN KANG</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Advanced Display Research Center, Department of Information Display, Kyung Hee University</s1><s2>Seoul 130-701</s2><s3>KOR</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Corée du Sud</country><placeName><settlement type="city">Séoul</settlement></placeName></affiliation></author><author><name>JIN JANG</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Advanced Display Research Center, Department of Information Display, Kyung Hee University</s1><s2>Seoul 130-701</s2><s3>KOR</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Corée du Sud</country><placeName><settlement type="city">Séoul</settlement></placeName></affiliation></author></titleStmt><publicationStmt><idno type="inist">12-0241693</idno><date when="2012">2012</date><idno type="stanalyst">PASCAL 12-0241693 INIST</idno><idno type="RBID">Pascal:12-0241693</idno><idno type="wicri:Area/Main/Corpus">001C90</idno><idno type="wicri:Area/Main/Repository">002101</idno></publicationStmt><seriesStmt><idno type="ISSN">0741-3106</idno><title level="j" type="abbreviated">IEEE electron device lett.</title><title level="j" type="main">IEEE electron device letters</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Active system</term><term>Amorphous material</term><term>Gallium oxide</term><term>Indium oxide</term><term>Integrated circuit</term><term>Interconnection</term><term>On off effect</term><term>Switching</term><term>Thin film transistor</term><term>Via hole</term><term>Zinc oxide</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Transistor couche mince</term><term>Matériau amorphe</term><term>Commutation</term><term>Effet on off</term><term>Système actif</term><term>Trou interconnexion</term><term>Oxyde d'indium</term><term>Oxyde de gallium</term><term>Oxyde de zinc</term><term>Interconnexion</term><term>Circuit intégré</term></keywords><keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Matériau amorphe</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">We report a three-mask-processed coplanar amorphous-InGaZnO thin-film transistor (TFT) with equal offsets at the source and drain sides. TFTs with offset lengths ranging from 1.5 to 4.0 μm exhibit good switching characteristics with turn-on voltage around -1.6 V, gate swing of ˜0.1 V/decade, and on/off current ratio > 10<sup>5</sup>. While gate swing and turn-on voltage are independent of the offset length, the field-effect mobility decreases from 2.4 to 0.5 cm<sup>2</sup>/V.s as the offset length increases from 1.5 to 4 μm. This coplanar TFT is suitable for cost-effective active-matrix displays with minimal kickback/feedthrough voltage.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0741-3106</s0></fA01><fA02 i1="01"><s0>EDLEDZ</s0></fA02><fA03 i2="1"><s0>IEEE electron device lett.</s0></fA03><fA05><s2>33</s2></fA05><fA06><s2>6</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets</s1></fA08><fA11 i1="01" i2="1"><s1>UNG GI LEE</s1></fA11><fA11 i1="02" i2="1"><s1>MATIVENGA (Mallory)</s1></fA11><fA11 i1="03" i2="1"><s1>DONG HAN KANG</s1></fA11><fA11 i1="04" i2="1"><s1>JIN JANG</s1></fA11><fA14 i1="01"><s1>Advanced Display Research Center, Department of Information Display, Kyung Hee University</s1><s2>Seoul 130-701</s2><s3>KOR</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></fA14><fA20><s1>812-814</s1></fA20><fA21><s1>2012</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>222V</s2><s5>354000507755360240</s5></fA43><fA44><s0>0000</s0><s1>© 2012 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>15 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>12-0241693</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>IEEE electron device letters</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>We report a three-mask-processed coplanar amorphous-InGaZnO thin-film transistor (TFT) with equal offsets at the source and drain sides. TFTs with offset lengths ranging from 1.5 to 4.0 μm exhibit good switching characteristics with turn-on voltage around -1.6 V, gate swing of ˜0.1 V/decade, and on/off current ratio > 10<sup>5</sup>. While gate swing and turn-on voltage are independent of the offset length, the field-effect mobility decreases from 2.4 to 0.5 cm<sup>2</sup>/V.s as the offset length increases from 1.5 to 4 μm. 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