InforLorV4, PascalFrancis, Corpus, bibRecord, 000893

Digital hardware implementation of 2D compatible neural networks

Identifieur interne : 000893 ( PascalFrancis/Corpus ); précédent : 000892; suivant : 000894

Digital hardware implementation of 2D compatible neural networks

Auteurs : Bernard Girau

Source :

RBID : Pascal:02-0119636

Descripteurs français

Pascal (Inist)
- Conception circuit, Circuit numérique, Architecture reconfigurable, Réseau porte programmable, Algorithme parallèle, Intelligence artificielle, Réseau neuronal.

English descriptors

KwdEn :
- Artificial intelligence, Circuit design, Digital circuit, Field programmable gate array, Neural network, Parallel algorithm, Reconfigurable architectures.

Notice en format standard (ISO 2709)

Pour connaître la documentation sur le format Inist Standard.

A08	`01`	`1`	`ENG`	`@1 Digital hardware implementation of 2D compatible neural networks`
A09	`01`	`1`	`ENG`	`@1 IJCNN 2000 : international joint conference on neural networks : neural computing : new challenges and perspectives for the new millennium : Como, 24-27 July 2000`
A11	`01`	`1`		`@1 GIRAU (Bernard)`
A12	`01`	`1`		`@1 AMARI (Shun-Ichi) @9 ed.`
A12	`02`	`1`		`@1 GILES (C. Lee) @9 ed.`
A12	`03`	`1`		`@1 GORI (Marco) @9 ed.`
A12	`04`	`1`		`@1 PIURI (Vincenzo) @9 ed.`
A14	`01`			`@1 LORIA, INRIA-Lorraine, campus scientifique BP 239 @2 54506 Vandoeuvre-les-Nancy @3 FRA @Z 1 aut.`
A14	`02`			`@1 School of Computer Science, McGill University, 3480 University street @2 Montreal, Quebec H3A 2A7 @3 CAN @Z 1 aut.`
A20				`@2 Vol3.506-511`
A21				`@1 2000`
A23	`01`			`@0 ENG`
A25	`01`			`@1 IEEE Computer Society @2 Los Alamitos CA`
A26	`01`			`@0 0-7695-0619-4`
A30	`01`	`1`	`ENG`	`@1 IEEE-INNS-ENNS international joint conference on neural networks @3 Como ITA @4 2000-07-24`
A43	`01`			`@1 INIST @2 Y 33704 @5 354000097049261860`
A44				`@0 0000 @1 © 2002 INIST-CNRS. All rights reserved.`
A45				`@0 15 ref.`
A47	`01`	`1`		`@0 02-0119636`
A60				`@1 C`
A61				`@0 A`
A66	`01`			`@0 USA`
C02	`01`	`X`		`@0 001D02C06`
C02	`02`	`X`		`@0 001D03F06B`
C03	`01`	`X`	`FRE`	`@0 Conception circuit @5 01`
C03	`01`	`X`	`ENG`	`@0 Circuit design @5 01`
C03	`01`	`X`	`SPA`	`@0 Diseño circuito @5 01`
C03	`02`	`X`	`FRE`	`@0 Circuit numérique @5 02`
C03	`02`	`X`	`ENG`	`@0 Digital circuit @5 02`
C03	`02`	`X`	`SPA`	`@0 Circuito numérico @5 02`
C03	`03`	`3`	`FRE`	`@0 Architecture reconfigurable @5 03`
C03	`03`	`3`	`ENG`	`@0 Reconfigurable architectures @5 03`
C03	`04`	`X`	`FRE`	`@0 Réseau porte programmable @5 04`
C03	`04`	`X`	`ENG`	`@0 Field programmable gate array @5 04`
C03	`04`	`X`	`SPA`	`@0 Red puerta programable @5 04`
C03	`05`	`X`	`FRE`	`@0 Algorithme parallèle @5 05`
C03	`05`	`X`	`ENG`	`@0 Parallel algorithm @5 05`
C03	`05`	`X`	`SPA`	`@0 Algoritmo paralelo @5 05`
C03	`06`	`X`	`FRE`	`@0 Intelligence artificielle @5 09`
C03	`06`	`X`	`ENG`	`@0 Artificial intelligence @5 09`
C03	`06`	`X`	`SPA`	`@0 Inteligencia artificial @5 09`
C03	`07`	`X`	`FRE`	`@0 Réseau neuronal @5 10`
C03	`07`	`X`	`ENG`	`@0 Neural network @5 10`
C03	`07`	`X`	`SPA`	`@0 Red neuronal @5 10`
N21				`@1 063`
N82				`@1 PSI`

Format Inist (serveur)

NO :	PASCAL 02-0119636 INIST
ET :	Digital hardware implementation of 2D compatible neural networks
AU :	GIRAU (Bernard); AMARI (Shun-Ichi); GILES (C. Lee); GORI (Marco); PIURI (Vincenzo)
AF :	LORIA, INRIA-Lorraine, campus scientifique BP 239/54506 Vandoeuvre-les-Nancy/France (1 aut.); School of Computer Science, McGill University, 3480 University street/Montreal, Quebec H3A 2A7/Canada (1 aut.)
DT :	Congrès; Niveau analytique
SO :	IEEE-INNS-ENNS international joint conference on neural networks/2000-07-24/Como ITA; Etats-Unis; Los Alamitos CA: IEEE Computer Society; Da. 2000; Vol3.506-511; ISBN 0-7695-0619-4
LA :	Anglais
CC :	001D02C06; 001D03F06B
FD :	Conception circuit; Circuit numérique; Architecture reconfigurable; Réseau porte programmable; Algorithme parallèle; Intelligence artificielle; Réseau neuronal
ED :	Circuit design; Digital circuit; Reconfigurable architectures; Field programmable gate array; Parallel algorithm; Artificial intelligence; Neural network
SD :	Diseño circuito; Circuito numérico; Red puerta programable; Algoritmo paralelo; Inteligencia artificial; Red neuronal
LO :	INIST-Y 33704.354000097049261860
ID :	02-0119636

Links to Exploration step

Pascal:02-0119636

Le document en format XML

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<ET>Digital hardware implementation of 2D compatible neural networks</ET>
<AU>GIRAU (Bernard); AMARI (Shun-Ichi); GILES (C. Lee); GORI (Marco); PIURI (Vincenzo)</AU>
<AF>LORIA, INRIA-Lorraine, campus scientifique BP 239/54506 Vandoeuvre-les-Nancy/France (1 aut.); School of Computer Science, McGill University, 3480 University street/Montreal, Quebec H3A 2A7/Canada (1 aut.)</AF>
<DT>Congrès; Niveau analytique</DT>
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Digital hardware implementation of 2D compatible neural networks

Digital hardware implementation of 2D compatible neural networks

Source :

Descripteurs français

English descriptors

Notice en format standard (ISO 2709)

Format Inist (serveur)

Links to Exploration step

Le document en format XML

Pour manipuler ce document sous Unix (Dilib)

Pour mettre un lien sur cette page dans le réseau Wicri