Efficient satisfiability modulo theories via delayed theory combination
Identifieur interne :
000543 ( PascalFrancis/Corpus );
précédent :
000542;
suivant :
000544
Efficient satisfiability modulo theories via delayed theory combination
Auteurs : Marco Bozzano ;
Roberto Bruttomesso ;
Alessandro Cimatti ;
Tommi Junttila ;
Silvio Ranise ;
Peter Van Rossum ;
Roberto SebastianiSource :
-
Lecture notes in computer science [ 0302-9743 ] ; 2005.
RBID : Pascal:05-0349607
Descripteurs français
- Pascal (Inist)
- Retard,
Simultanéité informatique,
Logique propositionnelle,
Processeur pipeline,
Théorie preuve,
Vérification programme,
Prise décision,
Satisfiabilité,
Quantificateur,
Multitâche,
Niveau transfert registre,
Architecture logiciel,
Problème satisfiabilité,
Modélisation,
Logique booléenne,
Enumération,
Disjonction,
Analyse non convexe.
English descriptors
- KwdEn :
- Boolean logic,
Concurrency,
Decision making,
Delay,
Disjunction,
Enumeration,
Modeling,
Multithread,
Non convex analysis,
Pipeline processor,
Program verification,
Proof theory,
Propositional logic,
Quantifier,
Register transfer level,
Satisfiability,
Satisfiability problem,
Software architecture.
Abstract
The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T1 ========cup; T2 of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T1 U T2, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T1 U T2), called Delayed Theory Combination, which does not require a decision procedure for T1 ========cup; T2, but only individual decision procedures for T1 and T2, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison.
Notice en format standard (ISO 2709)
Pour connaître la documentation sur le format Inist Standard.
| pA |
| A01 | 01 | 1 | | @0 0302-9743 |
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| A05 | | | | @2 3576 |
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| A08 | 01 | 1 | ENG | @1 Efficient satisfiability modulo theories via delayed theory combination |
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| A09 | 01 | 1 | ENG | @1 CAV 2005 : computer aided verification : Edinburgh, 6-10 July 2005 |
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| A11 | 01 | 1 | | @1 BOZZANO (Marco) |
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| A11 | 02 | 1 | | @1 BRUTTOMESSO (Roberto) |
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| A11 | 03 | 1 | | @1 CIMATTI (Alessandro) |
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| A11 | 04 | 1 | | @1 JUNTTILA (Tommi) |
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| A11 | 05 | 1 | | @1 RANISE (Silvio) |
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| A11 | 06 | 1 | | @1 VAN ROSSUM (Peter) |
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| A11 | 07 | 1 | | @1 SEBASTIANI (Roberto) |
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| A12 | 01 | 1 | | @1 ETESSAMI (Kousha) @9 ed. |
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| A12 | 02 | 1 | | @1 RAJAMANI (Sriram K.) @9 ed. |
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| A14 | 01 | | | @1 ITC-IRST, Povo @2 Trento @3 ITA @Z 1 aut. @Z 2 aut. @Z 3 aut. |
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| A14 | 02 | | | @1 Helsinki University of Technology @3 FIN @Z 4 aut. |
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| A14 | 03 | | | @1 LORIA and INRIA-Lorraine @2 Villers les Nancy @3 FRA @Z 5 aut. |
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| A14 | 04 | | | @1 Radboud University Nijmegen @3 NLD @Z 6 aut. |
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| A14 | 05 | | | @1 DIT, University di Trento @3 ITA @Z 7 aut. |
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| A20 | | | | @1 335-349 |
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| A21 | | | | @1 2005 |
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| A23 | 01 | | | @0 ENG |
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| A26 | 01 | | | @0 3-540-27231-3 |
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| A43 | 01 | | | @1 INIST @2 16343 @5 354000124488910330 |
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| A44 | | | | @0 0000 @1 © 2005 INIST-CNRS. All rights reserved. |
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| A45 | | | | @0 29 ref. |
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| A47 | 01 | 1 | | @0 05-0349607 |
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| A60 | | | | @1 P @2 C |
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| A61 | | | | @0 A |
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| A64 | 01 | 1 | | @0 Lecture notes in computer science |
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| A66 | 01 | | | @0 DEU |
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| C01 | 01 | | ENG | @0 The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T1 ========cup; T2 of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T1 U T2, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T1 U T2), called Delayed Theory Combination, which does not require a decision procedure for T1 ========cup; T2, but only individual decision procedures for T1 and T2, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison. |
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| C02 | 01 | X | | @0 001D02B09 |
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| C03 | 01 | X | FRE | @0 Retard @5 06 |
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| C03 | 01 | X | ENG | @0 Delay @5 06 |
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| C03 | 01 | X | SPA | @0 Retraso @5 06 |
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| C03 | 02 | X | FRE | @0 Simultanéité informatique @5 07 |
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| C03 | 02 | X | ENG | @0 Concurrency @5 07 |
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| C03 | 02 | X | SPA | @0 Simultaneidad informatica @5 07 |
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| C03 | 03 | X | FRE | @0 Logique propositionnelle @5 08 |
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| C03 | 03 | X | ENG | @0 Propositional logic @5 08 |
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| C03 | 03 | X | SPA | @0 Lógica proposicional @5 08 |
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| C03 | 04 | X | FRE | @0 Processeur pipeline @5 09 |
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| C03 | 04 | X | ENG | @0 Pipeline processor @5 09 |
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| C03 | 04 | X | SPA | @0 Procesador oleoducto @5 09 |
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| C03 | 05 | X | FRE | @0 Théorie preuve @5 10 |
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| C03 | 05 | X | ENG | @0 Proof theory @5 10 |
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| C03 | 05 | X | SPA | @0 Teoría demonstración @5 10 |
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| C03 | 06 | X | FRE | @0 Vérification programme @5 11 |
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| C03 | 06 | X | ENG | @0 Program verification @5 11 |
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| C03 | 06 | X | SPA | @0 Verificación programa @5 11 |
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| C03 | 07 | X | FRE | @0 Prise décision @5 12 |
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| C03 | 07 | X | ENG | @0 Decision making @5 12 |
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| C03 | 07 | X | SPA | @0 Toma decision @5 12 |
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| C03 | 08 | X | FRE | @0 Satisfiabilité @5 18 |
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| C03 | 08 | X | ENG | @0 Satisfiability @5 18 |
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| C03 | 08 | X | SPA | @0 Satisfactibilidad @5 18 |
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| C03 | 09 | X | FRE | @0 Quantificateur @5 19 |
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| C03 | 09 | X | ENG | @0 Quantifier @5 19 |
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| C03 | 09 | X | SPA | @0 Cuantificador @5 19 |
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| C03 | 10 | X | FRE | @0 Multitâche @5 20 |
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| C03 | 10 | X | ENG | @0 Multithread @5 20 |
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| C03 | 10 | X | SPA | @0 Multitarea @5 20 |
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| C03 | 11 | X | FRE | @0 Niveau transfert registre @5 21 |
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| C03 | 11 | X | ENG | @0 Register transfer level @5 21 |
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| C03 | 11 | X | SPA | @0 Registro RTL @5 21 |
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| C03 | 12 | 3 | FRE | @0 Architecture logiciel @5 22 |
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| C03 | 12 | 3 | ENG | @0 Software architecture @5 22 |
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| C03 | 13 | X | FRE | @0 Problème satisfiabilité @5 23 |
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| C03 | 13 | X | ENG | @0 Satisfiability problem @5 23 |
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| C03 | 13 | X | SPA | @0 Problema satisfactibilidad @5 23 |
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| C03 | 14 | X | FRE | @0 Modélisation @5 24 |
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| C03 | 14 | X | ENG | @0 Modeling @5 24 |
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| C03 | 14 | X | SPA | @0 Modelización @5 24 |
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| C03 | 15 | X | FRE | @0 Logique booléenne @5 25 |
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| C03 | 15 | X | ENG | @0 Boolean logic @5 25 |
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| C03 | 15 | X | SPA | @0 Lógica booleana @5 25 |
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| C03 | 16 | X | FRE | @0 Enumération @5 26 |
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| C03 | 16 | X | ENG | @0 Enumeration @5 26 |
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| C03 | 16 | X | SPA | @0 Enumeración @5 26 |
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| C03 | 17 | X | FRE | @0 Disjonction @5 27 |
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| C03 | 17 | X | ENG | @0 Disjunction @5 27 |
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| C03 | 17 | X | SPA | @0 Disyunción @5 27 |
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| C03 | 18 | X | FRE | @0 Analyse non convexe @5 28 |
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| C03 | 18 | X | ENG | @0 Non convex analysis @5 28 |
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| C03 | 18 | X | SPA | @0 Análisis no convexo @5 28 |
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| N21 | | | | @1 241 |
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| N44 | 01 | | | @1 OTO |
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| N82 | | | | @1 OTO |
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| pR |
| A30 | 01 | 1 | ENG | @1 Computer aided verification. International conference @2 17 @3 Edinburgh GBR @4 2005-07-06 |
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Format Inist (serveur)
| NO : | PASCAL 05-0349607 INIST |
|---|
| ET : | Efficient satisfiability modulo theories via delayed theory combination |
|---|
| AU : | BOZZANO (Marco); BRUTTOMESSO (Roberto); CIMATTI (Alessandro); JUNTTILA (Tommi); RANISE (Silvio); VAN ROSSUM (Peter); SEBASTIANI (Roberto); ETESSAMI (Kousha); RAJAMANI (Sriram K.) |
|---|
| AF : | ITC-IRST, Povo/Trento/Italie (1 aut., 2 aut., 3 aut.); Helsinki University of Technology/Finlande (4 aut.); LORIA and INRIA-Lorraine/Villers les Nancy/France (5 aut.); Radboud University Nijmegen/Pays-Bas (6 aut.); DIT, University di Trento/Italie (7 aut.) |
|---|
| DT : | Publication en série; Congrès; Niveau analytique |
|---|
| SO : | Lecture notes in computer science; ISSN 0302-9743; Allemagne; Da. 2005; Vol. 3576; Pp. 335-349; Bibl. 29 ref. |
|---|
| LA : | Anglais |
|---|
| EA : | The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T1 ========cup; T2 of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T1 U T2, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T1 U T2), called Delayed Theory Combination, which does not require a decision procedure for T1 ========cup; T2, but only individual decision procedures for T1 and T2, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison. |
|---|
| CC : | 001D02B09 |
|---|
| FD : | Retard; Simultanéité informatique; Logique propositionnelle; Processeur pipeline; Théorie preuve; Vérification programme; Prise décision; Satisfiabilité; Quantificateur; Multitâche; Niveau transfert registre; Architecture logiciel; Problème satisfiabilité; Modélisation; Logique booléenne; Enumération; Disjonction; Analyse non convexe |
|---|
| ED : | Delay; Concurrency; Propositional logic; Pipeline processor; Proof theory; Program verification; Decision making; Satisfiability; Quantifier; Multithread; Register transfer level; Software architecture; Satisfiability problem; Modeling; Boolean logic; Enumeration; Disjunction; Non convex analysis |
|---|
| SD : | Retraso; Simultaneidad informatica; Lógica proposicional; Procesador oleoducto; Teoría demonstración; Verificación programa; Toma decision; Satisfactibilidad; Cuantificador; Multitarea; Registro RTL; Problema satisfactibilidad; Modelización; Lógica booleana; Enumeración; Disyunción; Análisis no convexo |
|---|
| LO : | INIST-16343.354000124488910330 |
|---|
| ID : | 05-0349607 |
|---|
Links to Exploration step
Pascal:05-0349607
Le document en format XML
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<idno type="ISSN">0302-9743</idno>
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</seriesStmt><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Boolean logic</term>
<term>Concurrency</term>
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<term>Disjunction</term>
<term>Enumeration</term>
<term>Modeling</term>
<term>Multithread</term>
<term>Non convex analysis</term>
<term>Pipeline processor</term>
<term>Program verification</term>
<term>Proof theory</term>
<term>Propositional logic</term>
<term>Quantifier</term>
<term>Register transfer level</term>
<term>Satisfiability</term>
<term>Satisfiability problem</term>
<term>Software architecture</term>
</keywords><keywords scheme="Pascal" xml:lang="fr"><term>Retard</term>
<term>Simultanéité informatique</term>
<term>Logique propositionnelle</term>
<term>Processeur pipeline</term>
<term>Théorie preuve</term>
<term>Vérification programme</term>
<term>Prise décision</term>
<term>Satisfiabilité</term>
<term>Quantificateur</term>
<term>Multitâche</term>
<term>Niveau transfert registre</term>
<term>Architecture logiciel</term>
<term>Problème satisfiabilité</term>
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<term>Logique booléenne</term>
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</keywords><front><div type="abstract" xml:lang="en">The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T<sub>1</sub>
========cup; T<sub>2</sub>
of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T<sub>1</sub>
U T<sub>2</sub>
, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T<sub>1</sub>
U T<sub>2</sub>
), called Delayed Theory Combination, which does not require a decision procedure for T<sub>1</sub>
========cup; T<sub>2</sub>
, but only individual decision procedures for T<sub>1</sub>
and T<sub>2</sub>
, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison.</div><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0302-9743</s0>
</fA01><fA05><s2>3576</s2>
</fA05><fA08 i1="01" i2="1" l="ENG"><s1>Efficient satisfiability modulo theories via delayed theory combination</s1>
</fA08><fA09 i1="01" i2="1" l="ENG"><s1>CAV 2005 : computer aided verification : Edinburgh, 6-10 July 2005</s1>
</fA09><fA11 i1="01" i2="1"><s1>BOZZANO (Marco)</s1>
</fA11><fA11 i1="02" i2="1"><s1>BRUTTOMESSO (Roberto)</s1>
</fA11><fA11 i1="03" i2="1"><s1>CIMATTI (Alessandro)</s1>
</fA11><fA11 i1="04" i2="1"><s1>JUNTTILA (Tommi)</s1>
</fA11><fA11 i1="05" i2="1"><s1>RANISE (Silvio)</s1>
</fA11><fA11 i1="06" i2="1"><s1>VAN ROSSUM (Peter)</s1>
</fA11><fA11 i1="07" i2="1"><s1>SEBASTIANI (Roberto)</s1>
</fA11><fA12 i1="01" i2="1"><s1>ETESSAMI (Kousha)</s1>
<s9>ed.</s9>
</fA12><fA12 i1="02" i2="1"><s1>RAJAMANI (Sriram K.)</s1>
<s9>ed.</s9>
</fA12><fA14 i1="01"><s1>ITC-IRST, Povo</s1>
<s2>Trento</s2>
<s3>ITA</s3>
<sZ>1 aut.</sZ>
<sZ>2 aut.</sZ>
<sZ>3 aut.</sZ>
</fA14><fA14 i1="02"><s1>Helsinki University of Technology</s1>
<s3>FIN</s3>
<sZ>4 aut.</sZ>
</fA14><fA14 i1="03"><s1>LORIA and INRIA-Lorraine</s1>
<s2>Villers les Nancy</s2>
<s3>FRA</s3>
<sZ>5 aut.</sZ>
</fA14><fA14 i1="04"><s1>Radboud University Nijmegen</s1>
<s3>NLD</s3>
<sZ>6 aut.</sZ>
</fA14><fA14 i1="05"><s1>DIT, University di Trento</s1>
<s3>ITA</s3>
<sZ>7 aut.</sZ>
</fA14><fA20><s1>335-349</s1>
</fA20><fA21><s1>2005</s1>
</fA21><fA23 i1="01"><s0>ENG</s0>
</fA23><fA26 i1="01"><s0>3-540-27231-3</s0>
</fA26><fA43 i1="01"><s1>INIST</s1>
<s2>16343</s2>
<s5>354000124488910330</s5>
</fA43><fA44><s0>0000</s0>
<s1>© 2005 INIST-CNRS. All rights reserved.</s1>
</fA44><fA45><s0>29 ref.</s0>
</fA45><fA47 i1="01" i2="1"><s0>05-0349607</s0>
</fA47><fA60><s1>P</s1>
<s2>C</s2>
</fA60><fA64 i1="01" i2="1"><s0>Lecture notes in computer science</s0>
</fA64><fA66 i1="01"><s0>DEU</s0>
</fA66><fC01 i1="01" l="ENG"><s0>The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T<sub>1</sub>
========cup; T<sub>2</sub>
of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T<sub>1</sub>
U T<sub>2</sub>
, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T<sub>1</sub>
U T<sub>2</sub>
), called Delayed Theory Combination, which does not require a decision procedure for T<sub>1</sub>
========cup; T<sub>2</sub>
, but only individual decision procedures for T<sub>1</sub>
and T<sub>2</sub>
, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison.</s0><fC02 i1="01" i2="X"><s0>001D02B09</s0>
</fC02><fC03 i1="01" i2="X" l="FRE"><s0>Retard</s0>
<s5>06</s5>
</fC03><fC03 i1="01" i2="X" l="ENG"><s0>Delay</s0>
<s5>06</s5>
</fC03><fC03 i1="01" i2="X" l="SPA"><s0>Retraso</s0>
<s5>06</s5>
</fC03><fC03 i1="02" i2="X" l="FRE"><s0>Simultanéité informatique</s0>
<s5>07</s5>
</fC03><fC03 i1="02" i2="X" l="ENG"><s0>Concurrency</s0>
<s5>07</s5>
</fC03><fC03 i1="02" i2="X" l="SPA"><s0>Simultaneidad informatica</s0>
<s5>07</s5>
</fC03><fC03 i1="03" i2="X" l="FRE"><s0>Logique propositionnelle</s0>
<s5>08</s5>
</fC03><fC03 i1="03" i2="X" l="ENG"><s0>Propositional logic</s0>
<s5>08</s5>
</fC03><fC03 i1="03" i2="X" l="SPA"><s0>Lógica proposicional</s0>
<s5>08</s5>
</fC03><fC03 i1="04" i2="X" l="FRE"><s0>Processeur pipeline</s0>
<s5>09</s5>
</fC03><fC03 i1="04" i2="X" l="ENG"><s0>Pipeline processor</s0>
<s5>09</s5>
</fC03><fC03 i1="04" i2="X" l="SPA"><s0>Procesador oleoducto</s0>
<s5>09</s5>
</fC03><fC03 i1="05" i2="X" l="FRE"><s0>Théorie preuve</s0>
<s5>10</s5>
</fC03><fC03 i1="05" i2="X" l="ENG"><s0>Proof theory</s0>
<s5>10</s5>
</fC03><fC03 i1="05" i2="X" l="SPA"><s0>Teoría demonstración</s0>
<s5>10</s5>
</fC03><fC03 i1="06" i2="X" l="FRE"><s0>Vérification programme</s0>
<s5>11</s5>
</fC03><fC03 i1="06" i2="X" l="ENG"><s0>Program verification</s0>
<s5>11</s5>
</fC03><fC03 i1="06" i2="X" l="SPA"><s0>Verificación programa</s0>
<s5>11</s5>
</fC03><fC03 i1="07" i2="X" l="FRE"><s0>Prise décision</s0>
<s5>12</s5>
</fC03><fC03 i1="07" i2="X" l="ENG"><s0>Decision making</s0>
<s5>12</s5>
</fC03><fC03 i1="07" i2="X" l="SPA"><s0>Toma decision</s0>
<s5>12</s5>
</fC03><fC03 i1="08" i2="X" l="FRE"><s0>Satisfiabilité</s0>
<s5>18</s5>
</fC03><fC03 i1="08" i2="X" l="ENG"><s0>Satisfiability</s0>
<s5>18</s5>
</fC03><fC03 i1="08" i2="X" l="SPA"><s0>Satisfactibilidad</s0>
<s5>18</s5>
</fC03><fC03 i1="09" i2="X" l="FRE"><s0>Quantificateur</s0>
<s5>19</s5>
</fC03><fC03 i1="09" i2="X" l="ENG"><s0>Quantifier</s0>
<s5>19</s5>
</fC03><fC03 i1="09" i2="X" l="SPA"><s0>Cuantificador</s0>
<s5>19</s5>
</fC03><fC03 i1="10" i2="X" l="FRE"><s0>Multitâche</s0>
<s5>20</s5>
</fC03><fC03 i1="10" i2="X" l="ENG"><s0>Multithread</s0>
<s5>20</s5>
</fC03><fC03 i1="10" i2="X" l="SPA"><s0>Multitarea</s0>
<s5>20</s5>
</fC03><fC03 i1="11" i2="X" l="FRE"><s0>Niveau transfert registre</s0>
<s5>21</s5>
</fC03><fC03 i1="11" i2="X" l="ENG"><s0>Register transfer level</s0>
<s5>21</s5>
</fC03><fC03 i1="11" i2="X" l="SPA"><s0>Registro RTL</s0>
<s5>21</s5>
</fC03><fC03 i1="12" i2="3" l="FRE"><s0>Architecture logiciel</s0>
<s5>22</s5>
</fC03><fC03 i1="12" i2="3" l="ENG"><s0>Software architecture</s0>
<s5>22</s5>
</fC03><fC03 i1="13" i2="X" l="FRE"><s0>Problème satisfiabilité</s0>
<s5>23</s5>
</fC03><fC03 i1="13" i2="X" l="ENG"><s0>Satisfiability problem</s0>
<s5>23</s5>
</fC03><fC03 i1="13" i2="X" l="SPA"><s0>Problema satisfactibilidad</s0>
<s5>23</s5>
</fC03><fC03 i1="14" i2="X" l="FRE"><s0>Modélisation</s0>
<s5>24</s5>
</fC03><fC03 i1="14" i2="X" l="ENG"><s0>Modeling</s0>
<s5>24</s5>
</fC03><fC03 i1="14" i2="X" l="SPA"><s0>Modelización</s0>
<s5>24</s5>
</fC03><fC03 i1="15" i2="X" l="FRE"><s0>Logique booléenne</s0>
<s5>25</s5>
</fC03><fC03 i1="15" i2="X" l="ENG"><s0>Boolean logic</s0>
<s5>25</s5>
</fC03><fC03 i1="15" i2="X" l="SPA"><s0>Lógica booleana</s0>
<s5>25</s5>
</fC03><fC03 i1="16" i2="X" l="FRE"><s0>Enumération</s0>
<s5>26</s5>
</fC03><fC03 i1="16" i2="X" l="ENG"><s0>Enumeration</s0>
<s5>26</s5>
</fC03><fC03 i1="16" i2="X" l="SPA"><s0>Enumeración</s0>
<s5>26</s5>
</fC03><fC03 i1="17" i2="X" l="FRE"><s0>Disjonction</s0>
<s5>27</s5>
</fC03><fC03 i1="17" i2="X" l="ENG"><s0>Disjunction</s0>
<s5>27</s5>
</fC03><fC03 i1="17" i2="X" l="SPA"><s0>Disyunción</s0>
<s5>27</s5>
</fC03><fC03 i1="18" i2="X" l="FRE"><s0>Analyse non convexe</s0>
<s5>28</s5>
</fC03><fC03 i1="18" i2="X" l="ENG"><s0>Non convex analysis</s0>
<s5>28</s5>
</fC03><fC03 i1="18" i2="X" l="SPA"><s0>Análisis no convexo</s0>
<s5>28</s5>
</fC03><fN21><s1>241</s1>
</fN21><fN44 i1="01"><s1>OTO</s1>
</fN44><fN82><s1>OTO</s1>
</fN82><pR><fA30 i1="01" i2="1" l="ENG"><s1>Computer aided verification. International conference</s1>
<s2>17</s2>
<s3>Edinburgh GBR</s3>
<s4>2005-07-06</s4>
</fA30><server><NO>PASCAL 05-0349607 INIST</NO>
<ET>Efficient satisfiability modulo theories via delayed theory combination</ET>
<AU>BOZZANO (Marco); BRUTTOMESSO (Roberto); CIMATTI (Alessandro); JUNTTILA (Tommi); RANISE (Silvio); VAN ROSSUM (Peter); SEBASTIANI (Roberto); ETESSAMI (Kousha); RAJAMANI (Sriram K.)</AU>
<AF>ITC-IRST, Povo/Trento/Italie (1 aut., 2 aut., 3 aut.); Helsinki University of Technology/Finlande (4 aut.); LORIA and INRIA-Lorraine/Villers les Nancy/France (5 aut.); Radboud University Nijmegen/Pays-Bas (6 aut.); DIT, University di Trento/Italie (7 aut.)</AF>
<DT>Publication en série; Congrès; Niveau analytique</DT>
<SO>Lecture notes in computer science; ISSN 0302-9743; Allemagne; Da. 2005; Vol. 3576; Pp. 335-349; Bibl. 29 ref.</SO>
<LA>Anglais</LA>
<EA>The problem of deciding the satisfiability of a quantifier-free formula with respect to a background theory, also known as Satisfiability Modulo Theories (SMT), is gaining increasing relevance in verification: representation capabilities beyond propositional logic allow for a natural modeling of real-world problems (e.g., pipeline and RTL circuits verification, proof obligations in software systems). In this paper, we focus on the case where the background theory is the combination T<sub>1</sub>
========cup; T<sub>2</sub>
of two simpler theories. Many SMT procedures combine a boolean model enumeration with a decision procedure for T<sub>1</sub>
U T<sub>2</sub>
, where conjunctions of literals can be decided by an integration schema such as Nelson-Oppen, via a structured exchange of interface formulae (e.g., equalities in the case of convex theories, disjunctions of equalities otherwise). We propose a new approach for SMT(T<sub>1</sub>
U T<sub>2</sub>
), called Delayed Theory Combination, which does not require a decision procedure for T<sub>1</sub>
========cup; T<sub>2</sub>
, but only individual decision procedures for T<sub>1</sub>
and T<sub>2</sub>
, which are directly integrated into the boolean model enumerator. This approach is much simpler and natural, allows each of the solvers to be implemented and optimized without taking into account the others, and it nicely encompasses the case of non-convex theories. We show the effectiveness of the approach by a thorough experimental comparison.</EA><CC>001D02B09</CC>
<FD>Retard; Simultanéité informatique; Logique propositionnelle; Processeur pipeline; Théorie preuve; Vérification programme; Prise décision; Satisfiabilité; Quantificateur; Multitâche; Niveau transfert registre; Architecture logiciel; Problème satisfiabilité; Modélisation; Logique booléenne; Enumération; Disjonction; Analyse non convexe</FD>
<ED>Delay; Concurrency; Propositional logic; Pipeline processor; Proof theory; Program verification; Decision making; Satisfiability; Quantifier; Multithread; Register transfer level; Software architecture; Satisfiability problem; Modeling; Boolean logic; Enumeration; Disjunction; Non convex analysis</ED>
<SD>Retraso; Simultaneidad informatica; Lógica proposicional; Procesador oleoducto; Teoría demonstración; Verificación programa; Toma decision; Satisfactibilidad; Cuantificador; Multitarea; Registro RTL; Problema satisfactibilidad; Modelización; Lógica booleana; Enumeración; Disyunción; Análisis no convexo</SD>
<LO>INIST-16343.354000124488910330</LO>
<ID>05-0349607</ID>
</server>
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