Test Design From System Level Specification
Identifieur interne : 00B565 ( Main/Exploration ); précédent : 00B564; suivant : 00B566Test Design From System Level Specification
Auteurs : Ousmane Koné [France] ; Richard Castanet [France]Source :
English descriptors
- mix :
Abstract
Some distributed systems require a high degree of reliability. On the one hand, industrials pay much for testing activity in order to detect possible faults during design and implementation of communication components. On the other hand, standards are now available and systems must be tested for conformance. This work results from the collaboration between different institutions. The paper is a contribution to testing methodology for software/hardware systems specified with the VHDL standard. The proposed methodology is based on the computation of behavioral part of VHDL model. Different test selection techniques can be applied to the behavioral part, and the target test system is also modelled in VHDL. Test experiment can be performed with VHDL simulation tools and this constitute a great interest of our approach.
Url:
Affiliations:
- France
- Grand Est, Lorraine (région)
- Nancy
- Institut national polytechnique de Lorraine, Université Nancy 2, Université de Lorraine
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Le document en format XML
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<front><div type="abstract" xml:lang="en">Some distributed systems require a high degree of reliability. On the one hand, industrials pay much for testing activity in order to detect possible faults during design and implementation of communication components. On the other hand, standards are now available and systems must be tested for conformance. This work results from the collaboration between different institutions. The paper is a contribution to testing methodology for software/hardware systems specified with the VHDL standard. The proposed methodology is based on the computation of behavioral part of VHDL model. Different test selection techniques can be applied to the behavioral part, and the target test system is also modelled in VHDL. Test experiment can be performed with VHDL simulation tools and this constitute a great interest of our approach.</div>
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