Test Design From System Level Specification
Identifieur interne : 004A59 ( Hal/Curation ); précédent : 004A58; suivant : 004A60Test Design From System Level Specification
Auteurs : Ousmane Koné [France] ; Richard Castanet [France]Source :
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Abstract
Some distributed systems require a high degree of reliability. On the one hand, industrials pay much for testing activity in order to detect possible faults during design and implementation of communication components. On the other hand, standards are now available and systems must be tested for conformance. This work results from the collaboration between different institutions. The paper is a contribution to testing methodology for software/hardware systems specified with the VHDL standard. The proposed methodology is based on the computation of behavioral part of VHDL model. Different test selection techniques can be applied to the behavioral part, and the target test system is also modelled in VHDL. Test experiment can be performed with VHDL simulation tools and this constitute a great interest of our approach.
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On the one hand, industrials pay much for testing activity in order to detect possible faults during design and implementation of communication components. On the other hand, standards are now available and systems must be tested for conformance. This work results from the collaboration between different institutions. The paper is a contribution to testing methodology for software/hardware systems specified with the VHDL standard. The proposed methodology is based on the computation of behavioral part of VHDL model. Different test selection techniques can be applied to the behavioral part, and the target test system is also modelled in VHDL. Test experiment can be performed with VHDL simulation tools and this constitute a great interest of our approach.</div></front></TEI><hal api="V3"><titleStmt><title xml:lang="en">Test Design From System Level Specification</title><author role="aut"><persName><forename type="first">Ousmane</forename><surname>Koné</surname></persName><email>kone@loria.fr</email><idno type="halauthor">129559</idno><orgName ref="#struct-364480"></orgName><affiliation ref="#struct-160"></affiliation></author><author role="aut"><persName><forename type="first">Richard</forename><surname>Castanet</surname></persName><email></email><idno type="halauthor">129560</idno><orgName ref="#struct-364481"></orgName><affiliation ref="#struct-3102"></affiliation></author><editor role="depositor"><persName><forename>Publications</forename><surname>Loria</surname></persName><email>publications@loria.fr</email></editor></titleStmt><editionStmt><edition n="v1" type="current"><date type="whenSubmitted">2006-09-25 17:01:37</date><date type="whenModified">2016-05-19 01:04:41</date><date type="whenReleased">2006-09-28 15:22:44</date><date type="whenProduced">1998</date></edition><respStmt><resp>contributor</resp><name key="108626"><persName><forename>Publications</forename><surname>Loria</surname></persName><email>publications@loria.fr</email></name></respStmt></editionStmt><publicationStmt><distributor>CCSD</distributor><idno type="halId">inria-00098452</idno><idno type="halUri">https://hal.inria.fr/inria-00098452</idno><idno type="halBibtex">kone:inria-00098452</idno><idno type="halRefHtml">International Conference on Parallel & Distributed Processing Techniques & Applications - PDPTA'98, 1998, Las Vegas, USA, 1, 1998</idno><idno type="halRef">International Conference on Parallel & Distributed Processing Techniques & Applications - PDPTA'98, 1998, Las Vegas, USA, 1, 1998</idno></publicationStmt><seriesStmt><idno type="stamp" n="INRIA">INRIA - Institut National de Recherche en Informatique et en Automatique</idno><idno type="stamp" n="LABRI">Laboratoire Bordelais de Recherche en Informatique</idno><idno type="stamp" n="CNRS">CNRS - Centre national de la recherche scientifique</idno><idno type="stamp" n="INPL">Institut National Polytechnique de Lorraine</idno><idno type="stamp" n="ENSEIRB">Ecole Nationale Supérieure d'Electronique, Informatique et Radiocommunications de Bordeaux</idno><idno type="stamp" n="UNIV-BORDEAUX">Université de Bordeaux</idno><idno type="stamp" n="LORIA2">Publications du LORIA</idno><idno type="stamp" n="LABO-LORIA-SET" p="LORIA">LABO-LORIA-SET</idno><idno type="stamp" n="LORIA">LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications</idno><idno type="stamp" n="TESTBORDEAUX">TESTBORDEAUX</idno><idno type="stamp" n="UNIV-LORRAINE">Université de Lorraine</idno></seriesStmt><notesStmt><note type="commentary">Colloque avec actes et comité de lecture. internationale.</note><note type="audience" n="2">International</note><note type="invited" n="0">No</note><note type="popular" n="0">No</note><note type="peer" n="1">Yes</note><note type="proceedings" n="1">Yes</note></notesStmt><sourceDesc><biblStruct><analytic><title xml:lang="en">Test Design From System Level Specification</title><author role="aut"><persName><forename type="first">Ousmane</forename><surname>Koné</surname></persName><email>kone@loria.fr</email><idno type="halAuthorId">129559</idno><orgName ref="#struct-364480"></orgName><affiliation ref="#struct-160"></affiliation></author><author role="aut"><persName><forename type="first">Richard</forename><surname>Castanet</surname></persName><idno type="halAuthorId">129560</idno><orgName ref="#struct-364481"></orgName><affiliation ref="#struct-3102"></affiliation></author></analytic><monogr><idno type="localRef">98-R-224 || kone98a</idno><meeting><title>International Conference on Parallel & Distributed Processing Techniques & Applications - PDPTA'98</title><date type="start">1998</date><settlement>Las Vegas, USA</settlement></meeting><respStmt><resp>conferenceOrganizer</resp><name>CSREA-USA</name></respStmt><imprint><biblScope unit="volume">1</biblScope><date type="datePub">1998</date></imprint></monogr></biblStruct></sourceDesc><profileDesc><langUsage><language ident="en">English</language></langUsage><textClass><keywords scheme="author"><term xml:lang="en">méthodologie de test</term><term xml:lang="en">standardization.</term><term xml:lang="en">testing methodology</term><term xml:lang="en">distributed software/hardware</term><term xml:lang="en">logiciel/matériel distribué</term><term xml:lang="en">normalisation</term></keywords><classCode scheme="halDomain" n="info.info-oh">Computer Science [cs]/Other [cs.OH]</classCode><classCode scheme="halTypology" n="COMM">Conference papers</classCode></textClass><abstract xml:lang="en">Some distributed systems require a high degree of reliability. On the one hand, industrials pay much for testing activity in order to detect possible faults during design and implementation of communication components. On the other hand, standards are now available and systems must be tested for conformance. This work results from the collaboration between different institutions. The paper is a contribution to testing methodology for software/hardware systems specified with the VHDL standard. The proposed methodology is based on the computation of behavioral part of VHDL model. Different test selection techniques can be applied to the behavioral part, and the target test system is also modelled in VHDL. Test experiment can be performed with VHDL simulation tools and this constitute a great interest of our approach.</abstract></profileDesc></hal></record>Pour manipuler ce document sous Unix (Dilib)
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