Few electron limit of n-type metal oxide semiconductor single electron transistors
Identifieur interne : 000116 ( Istex/Curation ); précédent : 000115; suivant : 000117Few electron limit of n-type metal oxide semiconductor single electron transistors
Auteurs : Enrico Prati [Italie] ; Marco De Michielis [Italie] ; Matteo Belli [Italie] ; Simone Cocco [Italie] ; Marco Fanciulli [Italie] ; Dharmraj Kotekar-Patil [Allemagne] ; Matthias Ruoff [Allemagne] ; Dieter P. Kern [Allemagne] ; David A. Wharam [Allemagne] ; Jan Verduijn [Pays-Bas, Australie] ; Giuseppe C. Tettamanzi [Pays-Bas, Australie] ; Sven Rogge [Pays-Bas, Australie] ; Benoit Roche [France] ; Romain Wacquez [France] ; Xavier Jehl [France] ; Maud Vinet [France] ; Marc Sanquer [France]Source :
- Nanotechnology [ 0957-4484 ] ; 2012-06-01.
Descripteurs français
- Wicri :
- topic : Nanotechnologie, Oxyde, Simulation.
English descriptors
- KwdEn :
- Accumulation channel, Addition energies, Addition energy, Appl, Central planes, Cmos, Cmos technology, Complementary metal oxide semiconductor, Coulomb, Drain contacts, Electron beam lithography, Electron density, Electron occupancy, Electronic transport, Gate length, Gate level patterning, Gate voltage, High addition energies, Interface roughness, Lett, Metal oxide silicon sets, Nanotechnology, Nanowire, Nitride spacers, Oxide, Oxide thickness, Phys, Quantum, Quantum circuits, Quantum transport, Room temperature, Silicon, Silicon dioxide, Silicon nanowire, Silicon quantum, Silicon thickness, Similar samples, Simulation, Single electron transistors, Threshold voltage, Transistor.
- Teeft :
- Accumulation channel, Addition energies, Addition energy, Appl, Central planes, Cmos, Cmos technology, Complementary metal oxide semiconductor, Coulomb, Drain contacts, Electron beam lithography, Electron density, Electron occupancy, Electronic transport, Gate length, Gate level patterning, Gate voltage, High addition energies, Interface roughness, Lett, Metal oxide silicon sets, Nanotechnology, Nanowire, Nitride spacers, Oxide, Oxide thickness, Phys, Quantum, Quantum circuits, Quantum transport, Room temperature, Silicon, Silicon dioxide, Silicon nanowire, Silicon quantum, Silicon thickness, Similar samples, Simulation, Single electron transistors, Threshold voltage, Transistor.
Abstract
We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10nm on 200mm wafers. The nominal channel size of 2020nm2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.
Url:
DOI: 10.1088/0957-4484/23/21/215204
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<author><name sortKey="Rogge, Sven" sort="Rogge, Sven" uniqKey="Rogge S" first="Sven" last="Rogge">Sven Rogge</name>
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<author><name sortKey="Roche, Benoit" sort="Roche, Benoit" uniqKey="Roche B" first="Benoit" last="Roche">Benoit Roche</name>
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<author><name sortKey="Wacquez, Romain" sort="Wacquez, Romain" uniqKey="Wacquez R" first="Romain" last="Wacquez">Romain Wacquez</name>
<affiliation wicri:level="1"><mods:affiliation>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble, France</mods:affiliation>
<country xml:lang="fr">France</country>
<wicri:regionArea>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble</wicri:regionArea>
</affiliation>
<affiliation wicri:level="1"><mods:affiliation>CEA-LETI Minatec Campus, 17 rue des Martyrs, F-38054, Grenoble Cedex 9, France</mods:affiliation>
<country xml:lang="fr">France</country>
<wicri:regionArea>CEA-LETI Minatec Campus, 17 rue des Martyrs, F-38054, Grenoble Cedex 9</wicri:regionArea>
</affiliation>
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<author><name sortKey="Jehl, Xavier" sort="Jehl, Xavier" uniqKey="Jehl X" first="Xavier" last="Jehl">Xavier Jehl</name>
<affiliation wicri:level="1"><mods:affiliation>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble, France</mods:affiliation>
<country xml:lang="fr">France</country>
<wicri:regionArea>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble</wicri:regionArea>
</affiliation>
</author>
<author><name sortKey="Vinet, Maud" sort="Vinet, Maud" uniqKey="Vinet M" first="Maud" last="Vinet">Maud Vinet</name>
<affiliation wicri:level="1"><mods:affiliation>CEA-LETI Minatec Campus, 17 rue des Martyrs, F-38054, Grenoble Cedex 9, France</mods:affiliation>
<country xml:lang="fr">France</country>
<wicri:regionArea>CEA-LETI Minatec Campus, 17 rue des Martyrs, F-38054, Grenoble Cedex 9</wicri:regionArea>
</affiliation>
</author>
<author><name sortKey="Sanquer, Marc" sort="Sanquer, Marc" uniqKey="Sanquer M" first="Marc" last="Sanquer">Marc Sanquer</name>
<affiliation wicri:level="1"><mods:affiliation>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble, France</mods:affiliation>
<country xml:lang="fr">France</country>
<wicri:regionArea>Service de Physique Statistique, Magntisme et Supraconductivit, Institut Nanosciences et Cryognie,Commissariat lnergie Atomique Grenoble and Universit Joseph Fourier, F-38054 Grenoble</wicri:regionArea>
</affiliation>
<affiliation wicri:level="1"><mods:affiliation>E-mail: marc.sanquer@cea.fr</mods:affiliation>
<country wicri:rule="url">France</country>
</affiliation>
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<monogr></monogr>
<series><title level="j">Nanotechnology</title>
<idno type="ISSN">0957-4484</idno>
<idno type="eISSN">1361-6528</idno>
<imprint><publisher>IOP Publishing</publisher>
<date type="published" when="2012-06-01">2012-06-01</date>
<biblScope unit="volume">23</biblScope>
<biblScope unit="issue">21</biblScope>
</imprint>
<idno type="ISSN">0957-4484</idno>
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<seriesStmt><idno type="ISSN">0957-4484</idno>
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<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Accumulation channel</term>
<term>Addition energies</term>
<term>Addition energy</term>
<term>Appl</term>
<term>Central planes</term>
<term>Cmos</term>
<term>Cmos technology</term>
<term>Complementary metal oxide semiconductor</term>
<term>Coulomb</term>
<term>Drain contacts</term>
<term>Electron beam lithography</term>
<term>Electron density</term>
<term>Electron occupancy</term>
<term>Electronic transport</term>
<term>Gate length</term>
<term>Gate level patterning</term>
<term>Gate voltage</term>
<term>High addition energies</term>
<term>Interface roughness</term>
<term>Lett</term>
<term>Metal oxide silicon sets</term>
<term>Nanotechnology</term>
<term>Nanowire</term>
<term>Nitride spacers</term>
<term>Oxide</term>
<term>Oxide thickness</term>
<term>Phys</term>
<term>Quantum</term>
<term>Quantum circuits</term>
<term>Quantum transport</term>
<term>Room temperature</term>
<term>Silicon</term>
<term>Silicon dioxide</term>
<term>Silicon nanowire</term>
<term>Silicon quantum</term>
<term>Silicon thickness</term>
<term>Similar samples</term>
<term>Simulation</term>
<term>Single electron transistors</term>
<term>Threshold voltage</term>
<term>Transistor</term>
</keywords>
<keywords scheme="Teeft" xml:lang="en"><term>Accumulation channel</term>
<term>Addition energies</term>
<term>Addition energy</term>
<term>Appl</term>
<term>Central planes</term>
<term>Cmos</term>
<term>Cmos technology</term>
<term>Complementary metal oxide semiconductor</term>
<term>Coulomb</term>
<term>Drain contacts</term>
<term>Electron beam lithography</term>
<term>Electron density</term>
<term>Electron occupancy</term>
<term>Electronic transport</term>
<term>Gate length</term>
<term>Gate level patterning</term>
<term>Gate voltage</term>
<term>High addition energies</term>
<term>Interface roughness</term>
<term>Lett</term>
<term>Metal oxide silicon sets</term>
<term>Nanotechnology</term>
<term>Nanowire</term>
<term>Nitride spacers</term>
<term>Oxide</term>
<term>Oxide thickness</term>
<term>Phys</term>
<term>Quantum</term>
<term>Quantum circuits</term>
<term>Quantum transport</term>
<term>Room temperature</term>
<term>Silicon</term>
<term>Silicon dioxide</term>
<term>Silicon nanowire</term>
<term>Silicon quantum</term>
<term>Silicon thickness</term>
<term>Similar samples</term>
<term>Simulation</term>
<term>Single electron transistors</term>
<term>Threshold voltage</term>
<term>Transistor</term>
</keywords>
<keywords scheme="Wicri" type="topic" xml:lang="fr"><term>Nanotechnologie</term>
<term>Oxyde</term>
<term>Simulation</term>
</keywords>
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<front><div type="abstract">We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10nm on 200mm wafers. The nominal channel size of 2020nm2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.</div>
</front>
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