Few electron limit of n-type metal oxide semiconductor single electron transistors
Identifieur interne : 000463 ( Istex/Checkpoint ); précédent : 000462; suivant : 000464Few electron limit of n-type metal oxide semiconductor single electron transistors
Auteurs : Enrico Prati [Italie] ; Marco De Michielis [Italie] ; Matteo Belli [Italie] ; Simone Cocco [Italie] ; Marco Fanciulli [Italie] ; Dharmraj Kotekar-Patil [Allemagne] ; Matthias Ruoff [Allemagne] ; Dieter P. Kern [Allemagne] ; David A. Wharam [Allemagne] ; Jan Verduijn [Pays-Bas, Australie] ; Giuseppe C. Tettamanzi [Pays-Bas, Australie] ; Sven Rogge [Pays-Bas, Australie] ; Benoit Roche [France] ; Romain Wacquez [France] ; Xavier Jehl [France] ; Maud Vinet [France] ; Marc Sanquer [France]Source :
- Nanotechnology [ 0957-4484 ] ; 2012-06-01.
Descripteurs français
- Wicri :
- topic : Nanotechnologie, Oxyde, Simulation.
English descriptors
- KwdEn :
- Accumulation channel, Addition energies, Addition energy, Appl, Central planes, Cmos, Cmos technology, Complementary metal oxide semiconductor, Coulomb, Drain contacts, Electron beam lithography, Electron density, Electron occupancy, Electronic transport, Gate length, Gate level patterning, Gate voltage, High addition energies, Interface roughness, Lett, Metal oxide silicon sets, Nanotechnology, Nanowire, Nitride spacers, Oxide, Oxide thickness, Phys, Quantum, Quantum circuits, Quantum transport, Room temperature, Silicon, Silicon dioxide, Silicon nanowire, Silicon quantum, Silicon thickness, Similar samples, Simulation, Single electron transistors, Threshold voltage, Transistor.
- Teeft :
- Accumulation channel, Addition energies, Addition energy, Appl, Central planes, Cmos, Cmos technology, Complementary metal oxide semiconductor, Coulomb, Drain contacts, Electron beam lithography, Electron density, Electron occupancy, Electronic transport, Gate length, Gate level patterning, Gate voltage, High addition energies, Interface roughness, Lett, Metal oxide silicon sets, Nanotechnology, Nanowire, Nitride spacers, Oxide, Oxide thickness, Phys, Quantum, Quantum circuits, Quantum transport, Room temperature, Silicon, Silicon dioxide, Silicon nanowire, Silicon quantum, Silicon thickness, Similar samples, Simulation, Single electron transistors, Threshold voltage, Transistor.
Abstract
We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10nm on 200mm wafers. The nominal channel size of 2020nm2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.
Url:
DOI: 10.1088/0957-4484/23/21/215204
Affiliations:
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Links to Exploration step
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<front><div type="abstract">We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10nm on 200mm wafers. The nominal channel size of 2020nm2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.</div>
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<name sortKey="Tettamanzi, Giuseppe C" sort="Tettamanzi, Giuseppe C" uniqKey="Tettamanzi G" first="Giuseppe C" last="Tettamanzi">Giuseppe C. Tettamanzi</name>
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<country name="Australie"><noRegion><name sortKey="Verduijn, Jan" sort="Verduijn, Jan" uniqKey="Verduijn J" first="Jan" last="Verduijn">Jan Verduijn</name>
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<name sortKey="Rogge, Sven" sort="Rogge, Sven" uniqKey="Rogge S" first="Sven" last="Rogge">Sven Rogge</name>
<name sortKey="Tettamanzi, Giuseppe C" sort="Tettamanzi, Giuseppe C" uniqKey="Tettamanzi G" first="Giuseppe C" last="Tettamanzi">Giuseppe C. Tettamanzi</name>
</country>
<country name="France"><region name="Auvergne-Rhône-Alpes"><name sortKey="Roche, Benoit" sort="Roche, Benoit" uniqKey="Roche B" first="Benoit" last="Roche">Benoit Roche</name>
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<name sortKey="Jehl, Xavier" sort="Jehl, Xavier" uniqKey="Jehl X" first="Xavier" last="Jehl">Xavier Jehl</name>
<name sortKey="Sanquer, Marc" sort="Sanquer, Marc" uniqKey="Sanquer M" first="Marc" last="Sanquer">Marc Sanquer</name>
<name sortKey="Sanquer, Marc" sort="Sanquer, Marc" uniqKey="Sanquer M" first="Marc" last="Sanquer">Marc Sanquer</name>
<name sortKey="Vinet, Maud" sort="Vinet, Maud" uniqKey="Vinet M" first="Maud" last="Vinet">Maud Vinet</name>
<name sortKey="Wacquez, Romain" sort="Wacquez, Romain" uniqKey="Wacquez R" first="Romain" last="Wacquez">Romain Wacquez</name>
<name sortKey="Wacquez, Romain" sort="Wacquez, Romain" uniqKey="Wacquez R" first="Romain" last="Wacquez">Romain Wacquez</name>
</country>
</tree>
</affiliations>
</record>
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