OcrV1, PascalFrancis, Curation, bibRecord, 000648

Evaluation of the Impact of Superconducting Fault Current Limiters on Power System Network Protections Using a RTS-PHIL Methodology

Identifieur interne : 000648 ( PascalFrancis/Curation ); précédent : 000647; suivant : 000649

Evaluation of the Impact of Superconducting Fault Current Limiters on Power System Network Protections Using a RTS-PHIL Methodology

Auteurs : Mouhamadou Dione [Canada] ; Frédéric Sirois [Canada] ; Charles-Henri Bonnard [Canada]

Source :

IEEE transactions on applied superconductivity [ 1051-8223 ] ; 2011.

RBID : Pascal:11-0297332

Descripteurs français

Pascal (Inist)
- Dispositif supraconducteur, Limiteur courant défaut, Protection réseau électrique, Planification, Réseau électrique, Puissance électrique, Limiteur courant, Relais, Temps occupation, Système temps réel, Simulation HIL, Simulation circuit, Amplificateur puissance, Dispositif puissance, Matériel informatique, Circuit puissance, Structure petite échelle, Simulateur, Amplification linéaire, Surintensité, Reconnaissance optique caractère, Electronique puissance, Prévention dommage.

English descriptors

KwdEn :
- Circuit simulation, Computer hardware, Current limiter, Damage prevention, Electric power, Electrical network, Fault current limiters, Hardware in the loop simulation, Linear amplification, Occupation time, Optical character recognition, Overcurrent, Planning, Power amplifier, Power circuit, Power device, Power electronics, Power system protection, Real time system, Relay, Simulator, Small scale structure, Superconductor device.

Abstract

Planning the integration of a Superconducting Fault Current Limiter (SFCL) in an electric power network mainly consists in predicting the current limiting characteristics in any fault condition, in order to set the protection relays accordingly. Due to the very non linear behavior of the SFCL, modifications to the settings of existing protection relays are expected. To explore the potential changes, we used a Real-Time Simulation (RTS) methodology with Power-Hardware-In-the-Loop (PHIL) capabilities (i.e. circuit simulator coupled with power amplifiers for driving external physical power devices). The RTS-PHIL is a powerful approach that makes it possible to incorporate the actual transient reaction of the hardware under study without the need for developing a complicated numerical model, while the power system circuit, generally simpler in nature, can be purely simulated. In this project, the response of a commercial protection relay in the presence of a SFCL was investigated. Both the relay and a small scale shielded-core inductive limiter were coupled to the real time simulator (HYPERSIM) through single-phase linear power amplifiers and a variety of faults were applied. So far, this setup has allowed us to evaluate the impact of inserting a SFCL on overcurrent relays (OCR), in a simple radial distribution network. The results show that coordination has indeed to be slightly revised.

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A09	`01`	`1`	`ENG`	`@1 The 2010 Applied Superconductivity Conference, Washington, DC, August 1-6, 2010`
A11	`01`	`1`		`@1 DIONE (Mouhamadou)`
A11	`02`	`1`		`@1 SIROIS (Frédéric)`
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C01	`01`		`ENG`	@0 Planning the integration of a Superconducting Fault Current Limiter (SFCL) in an electric power network mainly consists in predicting the current limiting characteristics in any fault condition, in order to set the protection relays accordingly. Due to the very non linear behavior of the SFCL, modifications to the settings of existing protection relays are expected. To explore the potential changes, we used a Real-Time Simulation (RTS) methodology with Power-Hardware-In-the-Loop (PHIL) capabilities (i.e. circuit simulator coupled with power amplifiers for driving external physical power devices). The RTS-PHIL is a powerful approach that makes it possible to incorporate the actual transient reaction of the hardware under study without the need for developing a complicated numerical model, while the power system circuit, generally simpler in nature, can be purely simulated. In this project, the response of a commercial protection relay in the presence of a SFCL was investigated. Both the relay and a small scale shielded-core inductive limiter were coupled to the real time simulator (HYPERSIM) through single-phase linear power amplifiers and a variety of faults were applied. So far, this setup has allowed us to evaluate the impact of inserting a SFCL on overcurrent relays (OCR), in a simple radial distribution network. The results show that coordination has indeed to be slightly revised.
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C03	`09`	`X`	`FRE`	`@0 Temps occupation @5 09`
C03	`09`	`X`	`ENG`	`@0 Occupation time @5 09`
C03	`09`	`X`	`SPA`	`@0 Tiempo ocupación @5 09`
C03	`10`	`X`	`FRE`	`@0 Système temps réel @5 10`
C03	`10`	`X`	`ENG`	`@0 Real time system @5 10`
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C03	`18`	`X`	`FRE`	`@0 Simulateur @5 18`
C03	`18`	`X`	`ENG`	`@0 Simulator @5 18`
C03	`18`	`X`	`SPA`	`@0 Simulador @5 18`
C03	`19`	`X`	`FRE`	`@0 Amplification linéaire @5 19`
C03	`19`	`X`	`ENG`	`@0 Linear amplification @5 19`
C03	`19`	`X`	`SPA`	`@0 Amplificación lineal @5 19`
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A30	`01`	`1`	`ENG`	`@1 The Applied Superconductivity Conference (ASC 2010) @3 Washington USA @4 2010-08-01`

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Le document en format XML

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<front><div type="abstract" xml:lang="en">Planning the integration of a Superconducting Fault Current Limiter (SFCL) in an electric power network mainly consists in predicting the current limiting characteristics in any fault condition, in order to set the protection relays accordingly. Due to the very non linear behavior of the SFCL, modifications to the settings of existing protection relays are expected. To explore the potential changes, we used a Real-Time Simulation (RTS) methodology with Power-Hardware-In-the-Loop (PHIL) capabilities (i.e. circuit simulator coupled with power amplifiers for driving external physical power devices). The RTS-PHIL is a powerful approach that makes it possible to incorporate the actual transient reaction of the hardware under study without the need for developing a complicated numerical model, while the power system circuit, generally simpler in nature, can be purely simulated. In this project, the response of a commercial protection relay in the presence of a SFCL was investigated. Both the relay and a small scale shielded-core inductive limiter were coupled to the real time simulator (HYPERSIM) through single-phase linear power amplifiers and a variety of faults were applied. So far, this setup has allowed us to evaluate the impact of inserting a SFCL on overcurrent relays (OCR), in a simple radial distribution network. The results show that coordination has indeed to be slightly revised.</div>
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<s5>05</s5>
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<fC03 i1="06" i2="X" l="FRE"><s0>Puissance électrique</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="ENG"><s0>Electric power</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="X" l="SPA"><s0>Potencia eléctrica</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="X" l="FRE"><s0>Limiteur courant</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="ENG"><s0>Current limiter</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="SPA"><s0>Limitador corriente</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE"><s0>Relais</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG"><s0>Relay</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA"><s0>Relé</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE"><s0>Temps occupation</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG"><s0>Occupation time</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA"><s0>Tiempo ocupación</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE"><s0>Système temps réel</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG"><s0>Real time system</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA"><s0>Sistema tiempo real</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="X" l="FRE"><s0>Simulation HIL</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="ENG"><s0>Hardware in the loop simulation</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="SPA"><s0>Simulación HIL</s0>
<s5>11</s5>
</fC03>
<fC03 i1="12" i2="3" l="FRE"><s0>Simulation circuit</s0>
<s5>12</s5>
</fC03>
<fC03 i1="12" i2="3" l="ENG"><s0>Circuit simulation</s0>
<s5>12</s5>
</fC03>
<fC03 i1="13" i2="X" l="FRE"><s0>Amplificateur puissance</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="ENG"><s0>Power amplifier</s0>
<s5>13</s5>
</fC03>
<fC03 i1="13" i2="X" l="SPA"><s0>Amplificador potencia</s0>
<s5>13</s5>
</fC03>
<fC03 i1="14" i2="X" l="FRE"><s0>Dispositif puissance</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="ENG"><s0>Power device</s0>
<s5>14</s5>
</fC03>
<fC03 i1="14" i2="X" l="SPA"><s0>Dispositivo potencia</s0>
<s5>14</s5>
</fC03>
<fC03 i1="15" i2="X" l="FRE"><s0>Matériel informatique</s0>
<s5>15</s5>
</fC03>
<fC03 i1="15" i2="X" l="ENG"><s0>Computer hardware</s0>
<s5>15</s5>
</fC03>
<fC03 i1="15" i2="X" l="SPA"><s0>Hardware</s0>
<s5>15</s5>
</fC03>
<fC03 i1="16" i2="X" l="FRE"><s0>Circuit puissance</s0>
<s5>16</s5>
</fC03>
<fC03 i1="16" i2="X" l="ENG"><s0>Power circuit</s0>
<s5>16</s5>
</fC03>
<fC03 i1="16" i2="X" l="SPA"><s0>Circuito potencia</s0>
<s5>16</s5>
</fC03>
<fC03 i1="17" i2="X" l="FRE"><s0>Structure petite échelle</s0>
<s5>17</s5>
</fC03>
<fC03 i1="17" i2="X" l="ENG"><s0>Small scale structure</s0>
<s5>17</s5>
</fC03>
<fC03 i1="17" i2="X" l="SPA"><s0>Estructura pequeña escala</s0>
<s5>17</s5>
</fC03>
<fC03 i1="18" i2="X" l="FRE"><s0>Simulateur</s0>
<s5>18</s5>
</fC03>
<fC03 i1="18" i2="X" l="ENG"><s0>Simulator</s0>
<s5>18</s5>
</fC03>
<fC03 i1="18" i2="X" l="SPA"><s0>Simulador</s0>
<s5>18</s5>
</fC03>
<fC03 i1="19" i2="X" l="FRE"><s0>Amplification linéaire</s0>
<s5>19</s5>
</fC03>
<fC03 i1="19" i2="X" l="ENG"><s0>Linear amplification</s0>
<s5>19</s5>
</fC03>
<fC03 i1="19" i2="X" l="SPA"><s0>Amplificación lineal</s0>
<s5>19</s5>
</fC03>
<fC03 i1="20" i2="X" l="FRE"><s0>Surintensité</s0>
<s5>20</s5>
</fC03>
<fC03 i1="20" i2="X" l="ENG"><s0>Overcurrent</s0>
<s5>20</s5>
</fC03>
<fC03 i1="20" i2="X" l="SPA"><s0>Sobreintensidad</s0>
<s5>20</s5>
</fC03>
<fC03 i1="21" i2="X" l="FRE"><s0>Reconnaissance optique caractère</s0>
<s5>21</s5>
</fC03>
<fC03 i1="21" i2="X" l="ENG"><s0>Optical character recognition</s0>
<s5>21</s5>
</fC03>
<fC03 i1="21" i2="X" l="SPA"><s0>Reconocimento óptico de caracteres</s0>
<s5>21</s5>
</fC03>
<fC03 i1="22" i2="X" l="FRE"><s0>Electronique puissance</s0>
<s5>46</s5>
</fC03>
<fC03 i1="22" i2="X" l="ENG"><s0>Power electronics</s0>
<s5>46</s5>
</fC03>
<fC03 i1="22" i2="X" l="SPA"><s0>Electrónica potencia</s0>
<s5>46</s5>
</fC03>
<fC03 i1="23" i2="X" l="FRE"><s0>Prévention dommage</s0>
<s5>47</s5>
</fC03>
<fC03 i1="23" i2="X" l="ENG"><s0>Damage prevention</s0>
<s5>47</s5>
</fC03>
<fC03 i1="23" i2="X" l="SPA"><s0>Prevención daño</s0>
<s5>47</s5>
</fC03>
<fN21><s1>206</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
<pR><fA30 i1="01" i2="1" l="ENG"><s1>The Applied Superconductivity Conference (ASC 2010)</s1>
<s3>Washington USA</s3>
<s4>2010-08-01</s4>
</fA30>
</pR>
</standard>
</inist>
</record>

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   |texte=   Evaluation of the Impact of Superconducting Fault Current Limiters on Power System Network Protections Using a RTS-PHIL Methodology
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Evaluation of the Impact of Superconducting Fault Current Limiters on Power System Network Protections Using a RTS-PHIL Methodology

Evaluation of the Impact of Superconducting Fault Current Limiters on Power System Network Protections Using a RTS-PHIL Methodology

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