A parallel architecture for relaxation operations
Identifieur interne : 003B78 ( Main/Merge ); précédent : 003B77; suivant : 003B79A parallel architecture for relaxation operations
Auteurs : Masaru Kamada [Japon] ; Kazuo Toraichi [Japon] ; Ryoichi Mori [Japon] ; Kazuhiko Yamamoto (informaticien) [Japon] ; Hiromitsu Yamada [Japon]Source :
- Pattern Recognition [ 0031-3203 ] ; 1987.
Abstract
Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.
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DOI: 10.1016/0031-3203(88)90025-8
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uniqKey="Yamada H" first="Hiromitsu" last="Yamada">Hiromitsu Yamada</name><affiliation wicri:level="1"><country xml:lang="fr">Japon</country><wicri:regionArea>Electrotechnical Laboratory, MITI, 1-1 Umezono, Sakura, Niihari, Ibaraki</wicri:regionArea><wicri:noRegion>Ibaraki</wicri:noRegion></affiliation></author></analytic><monogr></monogr><series><title level="j">Pattern Recognition</title><title level="j" type="abbrev">PR</title><idno type="ISSN">0031-3203</idno><imprint><publisher>ELSEVIER</publisher><date type="published" when="1987">1987</date><biblScope unit="volume">21</biblScope><biblScope unit="issue">2</biblScope><biblScope unit="page" from="175">175</biblScope><biblScope unit="page" to="181">181</biblScope></imprint><idno type="ISSN">0031-3203</idno></series><idno type="istex">5ABD96B8F016A7A1517C6CD04B0A4AB88CF7FDE1</idno><idno type="DOI">10.1016/0031-3203(88)90025-8</idno><idno type="PII">0031-3203(88)90025-8</idno></biblStruct></sourceDesc><seriesStmt><idno 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But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.</div></front></TEI></record>Pour manipuler ce document sous Unix (Dilib)
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