Hierarchical array processor system (HAP)
Identifieur interne : 002E52 ( Istex/Corpus ); précédent : 002E51; suivant : 002E53Hierarchical array processor system (HAP)
Auteurs : Shigeharu Momoi ; Shigeo Shimada ; Masamitsu Kobayashi ; Tsutomu IshikawaSource :
- Lecture Notes in Computer Science [ 0302-9743 ] ; 1986.
Abstract
Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.
Url:
DOI: 10.1007/3-540-16811-7_185
Links to Exploration step
ISTEX:71C6C3BD844441AA9A05632824089E0AFEE14BD2Le document en format XML
<record><TEI wicri:istexFullTextTei="biblStruct"><teiHeader><fileDesc><titleStmt><title xml:lang="en">Hierarchical array processor system (HAP)</title><author><name sortKey="Momoi, Shigeharu" sort="Momoi, Shigeharu" uniqKey="Momoi S" first="Shigeharu" last="Momoi">Shigeharu Momoi</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Shimada, Shigeo" sort="Shimada, Shigeo" uniqKey="Shimada S" first="Shigeo" last="Shimada">Shigeo Shimada</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Kobayashi, Masamitsu" sort="Kobayashi, Masamitsu" uniqKey="Kobayashi M" first="Masamitsu" last="Kobayashi">Masamitsu Kobayashi</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Ishikawa, Tsutomu" sort="Ishikawa, Tsutomu" uniqKey="Ishikawa T" first="Tsutomu" last="Ishikawa">Tsutomu Ishikawa</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:71C6C3BD844441AA9A05632824089E0AFEE14BD2</idno><date when="1986" year="1986">1986</date><idno type="doi">10.1007/3-540-16811-7_185</idno><idno type="url">https://api.istex.fr/document/71C6C3BD844441AA9A05632824089E0AFEE14BD2/fulltext/pdf</idno><idno type="wicri:Area/Istex/Corpus">002E52</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a" type="main" xml:lang="en">Hierarchical array processor system (HAP)</title><author><name sortKey="Momoi, Shigeharu" sort="Momoi, Shigeharu" uniqKey="Momoi S" first="Shigeharu" last="Momoi">Shigeharu Momoi</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Shimada, Shigeo" sort="Shimada, Shigeo" uniqKey="Shimada S" first="Shigeo" last="Shimada">Shigeo Shimada</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Kobayashi, Masamitsu" sort="Kobayashi, Masamitsu" uniqKey="Kobayashi M" first="Masamitsu" last="Kobayashi">Masamitsu Kobayashi</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author><author><name sortKey="Ishikawa, Tsutomu" sort="Ishikawa, Tsutomu" uniqKey="Ishikawa T" first="Tsutomu" last="Ishikawa">Tsutomu Ishikawa</name><affiliation><mods:affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</mods:affiliation></affiliation></author></analytic><monogr></monogr><series><title level="s">Lecture Notes in Computer Science</title><imprint><date>1986</date></imprint><idno type="ISSN">0302-9743</idno><idno type="eISSN">1611-3349</idno><idno type="ISSN">0302-9743</idno></series><idno type="istex">71C6C3BD844441AA9A05632824089E0AFEE14BD2</idno><idno type="DOI">10.1007/3-540-16811-7_185</idno><idno type="ChapterID">38</idno><idno type="ChapterID">Chap38</idno></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">0302-9743</idno></seriesStmt></fileDesc><profileDesc><textClass></textClass><langUsage><language ident="en">en</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</div></front></TEI><istex><corpusName>springer</corpusName><author><json:item><name>Shigeharu Momoi</name><affiliations><json:string>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</json:string></affiliations></json:item><json:item><name>Shigeo Shimada</name><affiliations><json:string>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</json:string></affiliations></json:item><json:item><name>Masamitsu Kobayashi</name><affiliations><json:string>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</json:string></affiliations></json:item><json:item><name>Tsutomu Ishikawa</name><affiliations><json:string>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</json:string></affiliations></json:item></author><language><json:string>eng</json:string></language><abstract>Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. 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The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</p></abstract><textClass><keywords scheme="Book Subject Collection"><list><label>SUCO11645</label><item><term>Computer Science</term></item></list></keywords></textClass><textClass><keywords scheme="Book Subject Group"><list><label>I</label><label>I13014</label><label>I12026</label><item><term>Computer Science</term></item><item><term>Processor Architectures</term></item><item><term>Arithmetic and Logic Structures</term></item></list></keywords></textClass></profileDesc><revisionDesc><change when="1986">Published</change><change xml:id="refBibs-istex" who="#ISTEX-API" when="2016-3-20">References added</change></revisionDesc></teiHeader></istex:fulltextTEI><json:item><original>false</original><mimetype>text/plain</mimetype><extension>txt</extension><uri>https://api.istex.fr/document/71C6C3BD844441AA9A05632824089E0AFEE14BD2/fulltext/txt</uri></json:item></fulltext><metadata><istex:metadataXml wicri:clean="Springer, Publisher found" wicri:toSee="no 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4.2)</ChapterCategory><ChapterFirstPage>311</ChapterFirstPage><ChapterLastPage>318</ChapterLastPage><ChapterCopyright><CopyrightHolderName>Springer-Verlag</CopyrightHolderName><CopyrightYear>1986</CopyrightYear></ChapterCopyright><ChapterHistory><OnlineDate><Year>2005</Year><Month>5</Month><Day>31</Day></OnlineDate></ChapterHistory><ChapterGrants Type="Regular"><MetadataGrant Grant="OpenAccess"></MetadataGrant><AbstractGrant Grant="OpenAccess"></AbstractGrant><BodyPDFGrant Grant="Restricted"></BodyPDFGrant><BodyHTMLGrant Grant="Restricted"></BodyHTMLGrant><BibliographyGrant Grant="Restricted"></BibliographyGrant><ESMGrant Grant="Restricted"></ESMGrant></ChapterGrants><ChapterContext><SeriesID>558</SeriesID><BookID>3540168117</BookID><BookTitle>CONPAR 86</BookTitle></ChapterContext></ChapterInfo><ChapterHeader><AuthorGroup><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Shigeharu</GivenName><FamilyName>Momoi</FamilyName></AuthorName></Author><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Shigeo</GivenName><FamilyName>Shimada</FamilyName></AuthorName></Author><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Masamitsu</GivenName><FamilyName>Kobayashi</FamilyName></AuthorName></Author><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Tsutomu</GivenName><FamilyName>Ishikawa</FamilyName></AuthorName></Author><Affiliation ID="Aff1"><OrgName>NIT Electrical Communications Laboratories</OrgName><OrgAddress><Street>Musashino-shi</Street><City>Tokyo</City><Country>Japan</Country></OrgAddress></Affiliation></AuthorGroup><Abstract ID="Abs1" Language="En"><Heading>Abstract</Heading><Para>A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</Para></Abstract></ChapterHeader><NoBody></NoBody></Chapter></Book></Series></Publisher></istex:document></istex:metadataXml><mods version="3.6"><titleInfo lang="en"><title>Hierarchical array processor system (HAP)</title></titleInfo><titleInfo type="alternative" contentType="CDATA" lang="en"><title>Hierarchical array processor system (HAP)</title></titleInfo><name type="personal"><namePart type="given">Shigeharu</namePart><namePart type="family">Momoi</namePart><affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Shigeo</namePart><namePart type="family">Shimada</namePart><affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Masamitsu</namePart><namePart type="family">Kobayashi</namePart><affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Tsutomu</namePart><namePart type="family">Ishikawa</namePart><affiliation>NIT Electrical Communications Laboratories, Musashino-shi, Tokyo, Japan</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre type="conference [eBooks]" displayLabel="ReviewPaper"></genre><originInfo><publisher>Springer Berlin Heidelberg</publisher><place><placeTerm type="text">Berlin, Heidelberg</placeTerm></place><dateIssued encoding="w3cdtf">1986</dateIssued><copyrightDate encoding="w3cdtf">1986</copyrightDate></originInfo><language><languageTerm type="code" authority="rfc3066">en</languageTerm><languageTerm type="code" authority="iso639-2b">eng</languageTerm></language><physicalDescription><internetMediaType>text/html</internetMediaType></physicalDescription><abstract lang="en">Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</abstract><relatedItem type="host"><titleInfo><title>CONPAR 86</title><subTitle>Conference on Algorithms and Hardware for Parallel Processing Aachen, September 17–19, 1986 Proceedings</subTitle></titleInfo><name type="personal"><namePart type="given">Wolfgang</namePart><namePart type="family">Händler</namePart><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Dieter</namePart><namePart type="family">Haupt</namePart><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Rolf</namePart><namePart type="family">Jeltsch</namePart><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Wilfried</namePart><namePart type="family">Juling</namePart><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Otto</namePart><namePart type="family">Lange</namePart><role><roleTerm type="text">editor</roleTerm></role></name><genre type="Book Series" displayLabel="Proceedings"></genre><originInfo><copyrightDate encoding="w3cdtf">1986</copyrightDate><issuance>monographic</issuance></originInfo><subject><genre>Book Subject Collection</genre><topic authority="SpringerSubjectCodes" authorityURI="SUCO11645">Computer Science</topic></subject><subject><genre>Book Subject Group</genre><topic authority="SpringerSubjectCodes" authorityURI="I">Computer Science</topic><topic authority="SpringerSubjectCodes" authorityURI="I13014">Processor Architectures</topic><topic authority="SpringerSubjectCodes" authorityURI="I12026">Arithmetic and Logic Structures</topic></subject><identifier type="DOI">10.1007/3-540-16811-7</identifier><identifier type="ISBN">978-3-540-16811-9</identifier><identifier type="eISBN">978-3-540-44856-3</identifier><identifier type="ISSN">0302-9743</identifier><identifier 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