Performance, optimization, and fitness: Connecting applications to architectures
Identifieur interne : 000786 ( Istex/Corpus ); précédent : 000785; suivant : 000787Performance, optimization, and fitness: Connecting applications to architectures
Auteurs : Mohammad A. Bhuiyan ; Melissa C. Smith ; Vivek K. PallipuramSource :
- Concurrency and Computation: Practice and Experience [ 1532-0626 ] ; 2011-07.
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Abstract
Recent trends involving multicore processors and graphical processing units (GPUs) focus on exploiting task‐ and thread‐level parallelism. In this paper, we have analyzed various aspects of the performance of these architectures including NVIDIA GPUs, and multicore processors such as Intel Xeon, AMD Opteron, IBM's Cell Broadband Engine. The case study used in this paper is a biological spiking neural network (SNN), implemented with the Izhikevich, Wilson, Morris–Lecar, and Hodgkin–Huxley neuron models. The four SNN models have varying requirements for communication and computation making them useful for performance analysis of the hardware platforms. We report and analyze the variation of performance with network (problem size) scaling, available optimization techniques and execution configuration. A Fitness performance model, that predicts the suitability of the architecture for accelerating an application, is proposed and verified with the SNN implementation results. The Roofline model, another existing performance model, has also been utilized to determine the hardware bottleneck(s) and attainable peak performance of the architectures. Significant speedups for the four SNN neuron models utilizing these architectures are reported; the maximum speedup of 574x was observed in our GPU implementation. Our results and analysis show that a proper match of architecture with algorithm complexity provides the best performance. Copyright © 2010 John Wiley & Sons, Ltd.
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DOI: 10.1002/cpe.1688
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<abstract lang="en">Recent trends involving multicore processors and graphical processing units (GPUs) focus on exploiting task‐ and thread‐level parallelism. In this paper, we have analyzed various aspects of the performance of these architectures including NVIDIA GPUs, and multicore processors such as Intel Xeon, AMD Opteron, IBM's Cell Broadband Engine. The case study used in this paper is a biological spiking neural network (SNN), implemented with the Izhikevich, Wilson, Morris–Lecar, and Hodgkin–Huxley neuron models. The four SNN models have varying requirements for communication and computation making them useful for performance analysis of the hardware platforms. We report and analyze the variation of performance with network (problem size) scaling, available optimization techniques and execution configuration. A Fitness performance model, that predicts the suitability of the architecture for accelerating an application, is proposed and verified with the SNN implementation results. The Roofline model, another existing performance model, has also been utilized to determine the hardware bottleneck(s) and attainable peak performance of the architectures. Significant speedups for the four SNN neuron models utilizing these architectures are reported; the maximum speedup of 574x was observed in our GPU implementation. Our results and analysis show that a proper match of architecture with algorithm complexity provides the best performance. Copyright © 2010 John Wiley & Sons, Ltd.</abstract>
<subject lang="en"><genre>keywords</genre>
<topic>performance</topic>
<topic>multicore</topic>
<topic>GPU</topic>
<topic>optimization</topic>
<topic>Fitness model</topic>
</subject>
<relatedItem type="host"><titleInfo><title>Concurrency and Computation: Practice and Experience</title>
</titleInfo>
<titleInfo type="abbreviated"><title>Concurrency Computat.: Pract. Exper.</title>
</titleInfo>
<genre type="journal">journal</genre>
<subject><genre>article-category</genre>
<topic>Research Article</topic>
</subject>
<identifier type="ISSN">1532-0626</identifier>
<identifier type="eISSN">1532-0634</identifier>
<identifier type="DOI">10.1002/(ISSN)1532-0634</identifier>
<identifier type="PublisherID">CPE</identifier>
<part><date>2011</date>
<detail type="volume"><caption>vol.</caption>
<number>23</number>
</detail>
<detail type="issue"><caption>no.</caption>
<number>10</number>
</detail>
<extent unit="pages"><start>1066</start>
<end>1100</end>
<total>35</total>
</extent>
</part>
</relatedItem>
<relatedItem type="preceding"><titleInfo><title>Concurrency: Practice and Experience</title>
</titleInfo>
<identifier type="ISSN">1040-3108</identifier>
<identifier type="ISSN">1096-9128</identifier>
<part><date point="end">2000</date>
<detail type="volume"><caption>last vol.</caption>
<number>12</number>
</detail>
<detail type="issue"><caption>last no.</caption>
<number>15</number>
</detail>
</part>
</relatedItem>
<identifier type="istex">E43C7B0758A3069211F596C690F59417BBC0471F</identifier>
<identifier type="DOI">10.1002/cpe.1688</identifier>
<identifier type="ArticleID">CPE1688</identifier>
<accessCondition type="use and reproduction" contentType="copyright">Copyright © 2010 John Wiley & Sons, Ltd.</accessCondition>
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<recordOrigin>John Wiley & Sons, Ltd.</recordOrigin>
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