Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
Identifieur interne : 000383 ( Istex/Corpus ); précédent : 000382; suivant : 000384Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
Auteurs : A. Laurenzano ; Mitesh Meswani ; Laura Carrington ; Allan Snavely ; M. Tikir ; Stephen PooleSource :
- Lecture Notes in Computer Science [ 0302-9743 ] ; 2011.
Abstract
Abstract: Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.
Url:
DOI: 10.1007/978-3-642-23400-2_9
Links to Exploration step
ISTEX:85C771693C049D6774CFC213948CA9939456C56ELe document en format XML
<record><TEI wicri:istexFullTextTei="biblStruct"><teiHeader><fileDesc><titleStmt><title xml:lang="en">Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title><author><name sortKey="Laurenzano, A" sort="Laurenzano, A" uniqKey="Laurenzano A" first="A." last="Laurenzano">A. Laurenzano</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: michaell@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Meswani, Mitesh" sort="Meswani, Mitesh" uniqKey="Meswani M" first="Mitesh" last="Meswani">Mitesh Meswani</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: mitesh@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Carrington, Laura" sort="Carrington, Laura" uniqKey="Carrington L" first="Laura" last="Carrington">Laura Carrington</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: lcarring@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Snavely, Allan" sort="Snavely, Allan" uniqKey="Snavely A" first="Allan" last="Snavely">Allan Snavely</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: allans@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Tikir, M" sort="Tikir, M" uniqKey="Tikir M" first="M." last="Tikir">M. Tikir</name><affiliation><mods:affiliation>Google, Inc, Mountain View, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: mustafa.m.tikir@gmail.com</mods:affiliation></affiliation></author><author><name sortKey="Poole, Stephen" sort="Poole, Stephen" uniqKey="Poole S" first="Stephen" last="Poole">Stephen Poole</name><affiliation><mods:affiliation>Oak Ridge National Laboratory, Oak Ridge, TN, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: spoole@ornl.gov</mods:affiliation></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:85C771693C049D6774CFC213948CA9939456C56E</idno><date when="2011" year="2011">2011</date><idno type="doi">10.1007/978-3-642-23400-2_9</idno><idno type="url">https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/fulltext/pdf</idno><idno type="wicri:Area/Istex/Corpus">000383</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a" type="main" xml:lang="en">Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title><author><name sortKey="Laurenzano, A" sort="Laurenzano, A" uniqKey="Laurenzano A" first="A." last="Laurenzano">A. Laurenzano</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: michaell@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Meswani, Mitesh" sort="Meswani, Mitesh" uniqKey="Meswani M" first="Mitesh" last="Meswani">Mitesh Meswani</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: mitesh@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Carrington, Laura" sort="Carrington, Laura" uniqKey="Carrington L" first="Laura" last="Carrington">Laura Carrington</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: lcarring@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Snavely, Allan" sort="Snavely, Allan" uniqKey="Snavely A" first="Allan" last="Snavely">Allan Snavely</name><affiliation><mods:affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: allans@sdsc.edu</mods:affiliation></affiliation></author><author><name sortKey="Tikir, M" sort="Tikir, M" uniqKey="Tikir M" first="M." last="Tikir">M. Tikir</name><affiliation><mods:affiliation>Google, Inc, Mountain View, CA, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: mustafa.m.tikir@gmail.com</mods:affiliation></affiliation></author><author><name sortKey="Poole, Stephen" sort="Poole, Stephen" uniqKey="Poole S" first="Stephen" last="Poole">Stephen Poole</name><affiliation><mods:affiliation>Oak Ridge National Laboratory, Oak Ridge, TN, United States of America</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: spoole@ornl.gov</mods:affiliation></affiliation></author></analytic><monogr></monogr><series><title level="s">Lecture Notes in Computer Science</title><imprint><date>2011</date></imprint><idno type="ISSN">0302-9743</idno><idno type="eISSN">1611-3349</idno><idno type="ISSN">0302-9743</idno></series><idno type="istex">85C771693C049D6774CFC213948CA9939456C56E</idno><idno type="DOI">10.1007/978-3-642-23400-2_9</idno><idno type="ChapterID">9</idno><idno type="ChapterID">Chap9</idno></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">0302-9743</idno></seriesStmt></fileDesc><profileDesc><textClass></textClass><langUsage><language ident="en">en</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Abstract: Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.</div></front></TEI><istex><corpusName>springer</corpusName><author><json:item><name>Michael A. Laurenzano</name><affiliations><json:string>San Diego Supercomputer Center, La Jolla, CA, United States of America</json:string><json:string>E-mail: michaell@sdsc.edu</json:string></affiliations></json:item><json:item><name>Mitesh Meswani</name><affiliations><json:string>San Diego Supercomputer Center, La Jolla, CA, United States of America</json:string><json:string>E-mail: mitesh@sdsc.edu</json:string></affiliations></json:item><json:item><name>Laura Carrington</name><affiliations><json:string>San Diego Supercomputer Center, La Jolla, CA, United States of America</json:string><json:string>E-mail: lcarring@sdsc.edu</json:string></affiliations></json:item><json:item><name>Allan Snavely</name><affiliations><json:string>San Diego Supercomputer Center, La Jolla, CA, United States of America</json:string><json:string>E-mail: allans@sdsc.edu</json:string></affiliations></json:item><json:item><name>Mustafa M. Tikir</name><affiliations><json:string>Google, Inc, Mountain View, CA, United States of America</json:string><json:string>E-mail: mustafa.m.tikir@gmail.com</json:string></affiliations></json:item><json:item><name>Stephen Poole</name><affiliations><json:string>Oak Ridge National Laboratory, Oak Ridge, TN, United States of America</json:string><json:string>E-mail: spoole@ornl.gov</json:string></affiliations></json:item></author><language><json:string>eng</json:string></language><originalGenre><json:string>OriginalPaper</json:string></originalGenre><abstract>Abstract: Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.</abstract><qualityIndicators><score>9.098</score><pdfVersion>1.6</pdfVersion><pdfPageSize>429.442 x 659.895 pts</pdfPageSize><refBibsNative>false</refBibsNative><keywordCount>0</keywordCount><abstractCharCount>1525</abstractCharCount><pdfWordCount>4730</pdfWordCount><pdfCharCount>28318</pdfCharCount><pdfPageCount>12</pdfPageCount><abstractWordCount>239</abstractWordCount></qualityIndicators><title>Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title><chapterId><json:string>9</json:string><json:string>Chap9</json:string></chapterId><genre><json:string>conference</json:string></genre><serie><editor><json:item><name>David Hutchison</name><affiliations><json:string>Lancaster University, Lancaster, UK</json:string></affiliations></json:item><json:item><name>Takeo Kanade</name><affiliations><json:string>Carnegie Mellon University, Pittsburgh, PA, USA</json:string></affiliations></json:item><json:item><name>Josef Kittler</name><affiliations><json:string>University of Surrey, Guildford, UK</json:string></affiliations></json:item><json:item><name>Jon M. Kleinberg</name><affiliations><json:string>Cornell University, Ithaca, NY, USA</json:string></affiliations></json:item><json:item><name>Friedemann Mattern</name><affiliations><json:string>ETH Zurich, Zurich, Switzerland</json:string></affiliations></json:item><json:item><name>John C. Mitchell</name><affiliations><json:string>Stanford University, Stanford, CA, USA</json:string></affiliations></json:item><json:item><name>Moni Naor</name><affiliations><json:string>Weizmann Institute of Science, Rehovot, Israel</json:string></affiliations></json:item><json:item><name>Oscar Nierstrasz</name><affiliations><json:string>University of Bern, Bern, Switzerland</json:string></affiliations></json:item><json:item><name>C. Pandu Rangan</name><affiliations><json:string>Indian Institute of Technology, Madras, India</json:string></affiliations></json:item><json:item><name>Bernhard Steffen</name><affiliations><json:string>University of Dortmund, Dortmund, Germany</json:string></affiliations></json:item><json:item><name>Madhu Sudan</name><affiliations><json:string>Massachusetts Institute of Technology, MA, USA</json:string></affiliations></json:item><json:item><name>Demetri Terzopoulos</name><affiliations><json:string>University of California, Los Angeles, CA, USA</json:string></affiliations></json:item><json:item><name>Doug Tygar</name><affiliations><json:string>University of California, Berkeley, CA, USA</json:string></affiliations></json:item><json:item><name>Moshe Y. Vardi</name><affiliations><json:string>Rice University, Houston, TX, USA</json:string></affiliations></json:item><json:item><name>Gerhard Weikum</name><affiliations><json:string>Max-Planck Institute of Computer Science, Saarbrücken, Germany</json:string></affiliations></json:item></editor><issn><json:string>0302-9743</json:string></issn><language><json:string>unknown</json:string></language><eissn><json:string>1611-3349</json:string></eissn><title>Lecture Notes in Computer Science</title><copyrightDate>2011</copyrightDate></serie><host><editor><json:item><name>Emmanuel Jeannot</name><affiliations><json:string>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</json:string><json:string>E-mail: emmanuel.jeannot@inria.fr</json:string></affiliations></json:item><json:item><name>Raymond Namyst</name><affiliations><json:string>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</json:string><json:string>E-mail: raymond.namyst@labri.fr</json:string></affiliations></json:item><json:item><name>Jean Roman</name><affiliations><json:string>Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</json:string><json:string>E-mail: jean.roman@inria.fr</json:string></affiliations></json:item></editor><subject><json:item><value>Computer Science</value></json:item><json:item><value>Computer Science</value></json:item><json:item><value>Computation by Abstract Devices</value></json:item><json:item><value>Programming Techniques</value></json:item><json:item><value>Programming Languages, Compilers, Interpreters</value></json:item><json:item><value>Numeric Computing</value></json:item><json:item><value>Special Purpose and Application-Based Systems</value></json:item><json:item><value>Operating Systems</value></json:item></subject><isbn><json:string>978-3-642-23399-9</json:string></isbn><language><json:string>unknown</json:string></language><eissn><json:string>1611-3349</json:string></eissn><title>Euro-Par 2011 Parallel Processing</title><bookId><json:string>978-3-642-23400-2</json:string></bookId><volume>6852</volume><pages><last>90</last><first>79</first></pages><issn><json:string>0302-9743</json:string></issn><genre><json:string>book-series</json:string></genre><eisbn><json:string>978-3-642-23400-2</json:string></eisbn><copyrightDate>2011</copyrightDate><doi><json:string>10.1007/978-3-642-23400-2</json:string></doi></host><publicationDate>2011</publicationDate><copyrightDate>2011</copyrightDate><doi><json:string>10.1007/978-3-642-23400-2_9</json:string></doi><id>85C771693C049D6774CFC213948CA9939456C56E</id><score>0.17424767</score><fulltext><json:item><original>true</original><mimetype>application/pdf</mimetype><extension>pdf</extension><uri>https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/fulltext/pdf</uri></json:item><json:item><original>false</original><mimetype>application/zip</mimetype><extension>zip</extension><uri>https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/fulltext/zip</uri></json:item><istex:fulltextTEI uri="https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/fulltext/tei"><teiHeader><fileDesc><titleStmt><title level="a" type="main" xml:lang="en">Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title><respStmt><resp>Références bibliographiques récupérées via GROBID</resp><name resp="ISTEX-API">ISTEX-API (INIST-CNRS)</name></respStmt></titleStmt><publicationStmt><authority>ISTEX</authority><publisher>Springer Berlin Heidelberg</publisher><pubPlace>Berlin, Heidelberg</pubPlace><availability><p>Springer-Verlag GmbH Berlin Heidelberg, 2011</p></availability><date>2011</date></publicationStmt><sourceDesc><biblStruct type="inbook"><analytic><title level="a" type="main" xml:lang="en">Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title><author xml:id="author-1"><persName><forename type="first">Michael</forename><surname>Laurenzano</surname></persName><email>michaell@sdsc.edu</email><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation></author><author xml:id="author-2"><persName><forename type="first">Mitesh</forename><surname>Meswani</surname></persName><email>mitesh@sdsc.edu</email><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation></author><author xml:id="author-3"><persName><forename type="first">Laura</forename><surname>Carrington</surname></persName><email>lcarring@sdsc.edu</email><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation></author><author xml:id="author-4"><persName><forename type="first">Allan</forename><surname>Snavely</surname></persName><email>allans@sdsc.edu</email><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation></author><author xml:id="author-5"><persName><forename type="first">Mustafa</forename><surname>Tikir</surname></persName><email>mustafa.m.tikir@gmail.com</email><affiliation>Google, Inc, Mountain View, CA, United States of America</affiliation></author><author xml:id="author-6"><persName><forename type="first">Stephen</forename><surname>Poole</surname></persName><email>spoole@ornl.gov</email><affiliation>Oak Ridge National Laboratory, Oak Ridge, TN, United States of America</affiliation></author></analytic><monogr><title level="m">Euro-Par 2011 Parallel Processing</title><title level="m" type="sub">17th International Conference, Euro-Par 2011, Bordeaux, France, August 29 - September 2, 2011, Proceedings, Part I</title><idno type="pISBN">978-3-642-23399-9</idno><idno type="eISBN">978-3-642-23400-2</idno><idno type="pISSN">0302-9743</idno><idno type="eISSN">1611-3349</idno><idno type="DOI">10.1007/978-3-642-23400-2</idno><idno type="book-ID">978-3-642-23400-2</idno><idno type="book-title-ID">272698</idno><idno type="book-sequence-number">6852</idno><idno type="book-volume-number">6852</idno><idno type="book-chapter-count">54</idno><editor><persName><forename type="first">Emmanuel</forename><surname>Jeannot</surname></persName><email>emmanuel.jeannot@inria.fr</email><affiliation>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation></editor><editor><persName><forename type="first">Raymond</forename><surname>Namyst</surname></persName><email>raymond.namyst@labri.fr</email><affiliation>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation></editor><editor><persName><forename type="first">Jean</forename><surname>Roman</surname></persName><email>jean.roman@inria.fr</email><affiliation>Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation></editor><imprint><publisher>Springer Berlin Heidelberg</publisher><pubPlace>Berlin, Heidelberg</pubPlace><date type="published" when="2011"></date><biblScope unit="volume">6852</biblScope><biblScope unit="page" from="79">79</biblScope><biblScope unit="page" to="90">90</biblScope></imprint></monogr><series><title level="s">Lecture Notes in Computer Science</title><editor><persName><forename type="first">David</forename><surname>Hutchison</surname></persName><affiliation>Lancaster University, Lancaster, UK</affiliation></editor><editor><persName><forename type="first">Takeo</forename><surname>Kanade</surname></persName><affiliation>Carnegie Mellon University, Pittsburgh, PA, USA</affiliation></editor><editor><persName><forename type="first">Josef</forename><surname>Kittler</surname></persName><affiliation>University of Surrey, Guildford, UK</affiliation></editor><editor><persName><forename type="first">Jon</forename><forename type="first">M.</forename><surname>Kleinberg</surname></persName><affiliation>Cornell University, Ithaca, NY, USA</affiliation></editor><editor><persName><forename type="first">Friedemann</forename><surname>Mattern</surname></persName><affiliation>ETH Zurich, Zurich, Switzerland</affiliation></editor><editor><persName><forename type="first">John</forename><forename type="first">C.</forename><surname>Mitchell</surname></persName><affiliation>Stanford University, Stanford, CA, USA</affiliation></editor><editor><persName><forename type="first">Moni</forename><surname>Naor</surname></persName><affiliation>Weizmann Institute of Science, Rehovot, Israel</affiliation></editor><editor><persName><forename type="first">Oscar</forename><surname>Nierstrasz</surname></persName><affiliation>University of Bern, Bern, Switzerland</affiliation></editor><editor><persName><forename type="first">C.</forename><surname>Pandu Rangan</surname></persName><affiliation>Indian Institute of Technology, Madras, India</affiliation></editor><editor><persName><forename type="first">Bernhard</forename><surname>Steffen</surname></persName><affiliation>University of Dortmund, Dortmund, Germany</affiliation></editor><editor><persName><forename type="first">Madhu</forename><surname>Sudan</surname></persName><affiliation>Massachusetts Institute of Technology, MA, USA</affiliation></editor><editor><persName><forename type="first">Demetri</forename><surname>Terzopoulos</surname></persName><affiliation>University of California, Los Angeles, CA, USA</affiliation></editor><editor><persName><forename type="first">Doug</forename><surname>Tygar</surname></persName><affiliation>University of California, Berkeley, CA, USA</affiliation></editor><editor><persName><forename type="first">Moshe</forename><forename type="first">Y.</forename><surname>Vardi</surname></persName><affiliation>Rice University, Houston, TX, USA</affiliation></editor><editor><persName><forename type="first">Gerhard</forename><surname>Weikum</surname></persName><affiliation>Max-Planck Institute of Computer Science, Saarbrücken, Germany</affiliation></editor><biblScope><date>2011</date></biblScope><idno type="pISSN">0302-9743</idno><idno type="eISSN">1611-3349</idno><idno type="series-Id">558</idno></series><idno type="istex">85C771693C049D6774CFC213948CA9939456C56E</idno><idno type="DOI">10.1007/978-3-642-23400-2_9</idno><idno type="ChapterID">9</idno><idno type="ChapterID">Chap9</idno></biblStruct></sourceDesc></fileDesc><profileDesc><creation><date>2011</date></creation><langUsage><language ident="en">en</language></langUsage><abstract xml:lang="en"><p>Abstract: Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.</p></abstract><textClass><keywords scheme="Book-Subject-Collection"><list><label>SUCO11645</label><item><term>Computer Science</term></item></list></keywords></textClass><textClass><keywords scheme="Book-Subject-Group"><list><label>I</label><label>I16013</label><label>I14010</label><label>I14037</label><label>I1701X</label><label>I13030</label><label>I14045</label><item><term>Computer Science</term></item><item><term>Computation by Abstract Devices</term></item><item><term>Programming Techniques</term></item><item><term>Programming Languages, Compilers, Interpreters</term></item><item><term>Numeric Computing</term></item><item><term>Special Purpose and Application-Based Systems</term></item><item><term>Operating Systems</term></item></list></keywords></textClass></profileDesc><revisionDesc><change when="2011">Published</change><change xml:id="refBibs-istex" who="#ISTEX-API" when="2016-09-22">References added</change></revisionDesc></teiHeader></istex:fulltextTEI><json:item><original>false</original><mimetype>text/plain</mimetype><extension>txt</extension><uri>https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/fulltext/txt</uri></json:item></fulltext><metadata><istex:metadataXml wicri:clean="Springer, Publisher found" wicri:toSee="no header"><istex:xmlDeclaration>version="1.0" encoding="UTF-8"</istex:xmlDeclaration><istex:docType PUBLIC="-//Springer-Verlag//DTD A++ V2.4//EN" URI="http://devel.springer.de/A++/V2.4/DTD/A++V2.4.dtd" name="istex:docType"></istex:docType><istex:document><Publisher><PublisherInfo><PublisherName>Springer Berlin Heidelberg</PublisherName><PublisherLocation>Berlin, Heidelberg</PublisherLocation></PublisherInfo><Series><SeriesInfo TocLevels="0" SeriesType="Series"><SeriesID>558</SeriesID><SeriesPrintISSN>0302-9743</SeriesPrintISSN><SeriesElectronicISSN>1611-3349</SeriesElectronicISSN><SeriesTitle Language="En">Lecture Notes in Computer Science</SeriesTitle></SeriesInfo><SeriesHeader><EditorGroup><Editor AffiliationIDS="Aff1"><EditorName DisplayOrder="Western"><GivenName>David</GivenName><FamilyName>Hutchison</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff2"><EditorName DisplayOrder="Western"><GivenName>Takeo</GivenName><FamilyName>Kanade</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff3"><EditorName DisplayOrder="Western"><GivenName>Josef</GivenName><FamilyName>Kittler</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff4"><EditorName DisplayOrder="Western"><GivenName>Jon</GivenName><GivenName>M.</GivenName><FamilyName>Kleinberg</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff5"><EditorName DisplayOrder="Western"><GivenName>Friedemann</GivenName><FamilyName>Mattern</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff6"><EditorName DisplayOrder="Western"><GivenName>John</GivenName><GivenName>C.</GivenName><FamilyName>Mitchell</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff7"><EditorName DisplayOrder="Western"><GivenName>Moni</GivenName><FamilyName>Naor</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff8"><EditorName DisplayOrder="Western"><GivenName>Oscar</GivenName><FamilyName>Nierstrasz</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff9"><EditorName DisplayOrder="Western"><GivenName>C.</GivenName><FamilyName>Pandu Rangan</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff10"><EditorName DisplayOrder="Western"><GivenName>Bernhard</GivenName><FamilyName>Steffen</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff11"><EditorName DisplayOrder="Western"><GivenName>Madhu</GivenName><FamilyName>Sudan</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff12"><EditorName DisplayOrder="Western"><GivenName>Demetri</GivenName><FamilyName>Terzopoulos</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff13"><EditorName DisplayOrder="Western"><GivenName>Doug</GivenName><FamilyName>Tygar</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff14"><EditorName DisplayOrder="Western"><GivenName>Moshe</GivenName><GivenName>Y.</GivenName><FamilyName>Vardi</FamilyName></EditorName></Editor><Editor AffiliationIDS="Aff15"><EditorName DisplayOrder="Western"><GivenName>Gerhard</GivenName><FamilyName>Weikum</FamilyName></EditorName></Editor><Affiliation ID="Aff1"><OrgName>Lancaster University</OrgName><OrgAddress><City>Lancaster</City><Country>UK</Country></OrgAddress></Affiliation><Affiliation ID="Aff2"><OrgName>Carnegie Mellon University</OrgName><OrgAddress><City>Pittsburgh</City><State>PA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff3"><OrgName>University of Surrey</OrgName><OrgAddress><City>Guildford</City><Country>UK</Country></OrgAddress></Affiliation><Affiliation ID="Aff4"><OrgName>Cornell University</OrgName><OrgAddress><City>Ithaca</City><State>NY</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff5"><OrgName>ETH Zurich</OrgName><OrgAddress><City>Zurich</City><Country>Switzerland</Country></OrgAddress></Affiliation><Affiliation ID="Aff6"><OrgName>Stanford University</OrgName><OrgAddress><City>Stanford</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff7"><OrgName>Weizmann Institute of Science</OrgName><OrgAddress><City>Rehovot</City><Country>Israel</Country></OrgAddress></Affiliation><Affiliation ID="Aff8"><OrgName>University of Bern</OrgName><OrgAddress><City>Bern</City><Country>Switzerland</Country></OrgAddress></Affiliation><Affiliation ID="Aff9"><OrgName>Indian Institute of Technology</OrgName><OrgAddress><City>Madras</City><Country>India</Country></OrgAddress></Affiliation><Affiliation ID="Aff10"><OrgName>University of Dortmund</OrgName><OrgAddress><City>Dortmund</City><Country>Germany</Country></OrgAddress></Affiliation><Affiliation ID="Aff11"><OrgName>Massachusetts Institute of Technology</OrgName><OrgAddress><State>MA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff12"><OrgName>University of California</OrgName><OrgAddress><City>Los Angeles</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff13"><OrgName>University of California</OrgName><OrgAddress><City>Berkeley</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff14"><OrgName>Rice University</OrgName><OrgAddress><City>Houston</City><State>TX</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff15"><OrgName>Max-Planck Institute of Computer Science</OrgName><OrgAddress><City>Saarbrücken</City><Country>Germany</Country></OrgAddress></Affiliation></EditorGroup></SeriesHeader><Book Language="En"><BookInfo Language="En" NumberingStyle="ContentOnly" NumberingDepth="2" OutputMedium="All" TocLevels="0" ContainsESM="No" BookProductType="Proceedings" MediaType="eBook"><BookID>978-3-642-23400-2</BookID><BookTitle>Euro-Par 2011 Parallel Processing</BookTitle><BookSubTitle>17th International Conference, Euro-Par 2011, Bordeaux, France, August 29 - September 2, 2011, Proceedings, Part I</BookSubTitle><BookVolumeNumber>6852</BookVolumeNumber><BookSequenceNumber>6852</BookSequenceNumber><BookDOI>10.1007/978-3-642-23400-2</BookDOI><BookTitleID>272698</BookTitleID><BookPrintISBN>978-3-642-23399-9</BookPrintISBN><BookElectronicISBN>978-3-642-23400-2</BookElectronicISBN><BookChapterCount>54</BookChapterCount><BookCopyright><CopyrightHolderName>Springer-Verlag GmbH Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2011</CopyrightYear></BookCopyright><BookSubjectGroup><BookSubject Type="Primary" Code="I">Computer Science</BookSubject><BookSubject Type="Secondary" Priority="1" Code="I16013">Computation by Abstract Devices</BookSubject><BookSubject Type="Secondary" Priority="2" Code="I14010">Programming Techniques</BookSubject><BookSubject Type="Secondary" Priority="3" Code="I14037">Programming Languages, Compilers, Interpreters</BookSubject><BookSubject Type="Secondary" Priority="4" Code="I1701X">Numeric Computing</BookSubject><BookSubject Type="Secondary" Priority="5" Code="I13030">Special Purpose and Application-Based Systems</BookSubject><BookSubject Type="Secondary" Priority="6" Code="I14045">Operating Systems</BookSubject><SubjectCollection Code="SUCO11645">Computer Science</SubjectCollection></BookSubjectGroup><BookContext><SeriesID>558</SeriesID></BookContext></BookInfo><BookHeader><EditorGroup><Editor AffiliationIDS="Aff16"><EditorName DisplayOrder="Western"><GivenName>Emmanuel</GivenName><FamilyName>Jeannot</FamilyName></EditorName><Contact><Email>emmanuel.jeannot@inria.fr</Email></Contact></Editor><Editor AffiliationIDS="Aff16"><EditorName DisplayOrder="Western"><GivenName>Raymond</GivenName><FamilyName>Namyst</FamilyName></EditorName><Contact><Email>raymond.namyst@labri.fr</Email></Contact></Editor><Editor AffiliationIDS="Aff17"><EditorName DisplayOrder="Western"><GivenName>Jean</GivenName><FamilyName>Roman</FamilyName></EditorName><Contact><Email>jean.roman@inria.fr</Email></Contact></Editor><Affiliation ID="Aff16"><OrgName>Equipe Runtime, INRIA Bordeaux Sud-Ouest</OrgName><OrgAddress><Postcode>33405</Postcode><City>Talence Cedex</City><Country>France</Country></OrgAddress></Affiliation><Affiliation ID="Aff17"><OrgName>Equipe HIEPACS, INRIA Bordeaux Sud-Ouest</OrgName><OrgAddress><Postcode>33405</Postcode><City>Talence Cedex</City><Country>France</Country></OrgAddress></Affiliation></EditorGroup></BookHeader><Part ID="Part2"><PartInfo TocLevels="0"><PartID>2</PartID><PartSequenceNumber>2</PartSequenceNumber><PartTitle>Topic 2: Performance Prediction and Evaluation</PartTitle><PartChapterCount>7</PartChapterCount><PartContext><SeriesID>558</SeriesID><BookTitle>Euro-Par 2011 Parallel Processing</BookTitle></PartContext></PartInfo><Chapter ID="Chap9" Language="En"><ChapterInfo ChapterType="OriginalPaper" NumberingStyle="ContentOnly" NumberingDepth="2" TocLevels="0" ContainsESM="No"><ChapterID>9</ChapterID><ChapterDOI>10.1007/978-3-642-23400-2_9</ChapterDOI><ChapterSequenceNumber>9</ChapterSequenceNumber><ChapterTitle Language="En">Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</ChapterTitle><ChapterFirstPage>79</ChapterFirstPage><ChapterLastPage>90</ChapterLastPage><ChapterCopyright><CopyrightHolderName>Springer-Verlag Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2011</CopyrightYear></ChapterCopyright><ChapterGrants Type="Regular"><MetadataGrant Grant="OpenAccess"></MetadataGrant><AbstractGrant Grant="OpenAccess"></AbstractGrant><BodyPDFGrant Grant="Restricted"></BodyPDFGrant><BodyHTMLGrant Grant="Restricted"></BodyHTMLGrant><BibliographyGrant Grant="Restricted"></BibliographyGrant><ESMGrant Grant="Restricted"></ESMGrant></ChapterGrants><ChapterContext><SeriesID>558</SeriesID><PartID>2</PartID><BookID>978-3-642-23400-2</BookID><BookTitle>Euro-Par 2011 Parallel Processing</BookTitle></ChapterContext></ChapterInfo><ChapterHeader><AuthorGroup><Author AffiliationIDS="Aff18"><AuthorName DisplayOrder="Western"><GivenName>Michael</GivenName><GivenName>A.</GivenName><FamilyName>Laurenzano</FamilyName></AuthorName><Contact><Email>michaell@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff18"><AuthorName DisplayOrder="Western"><GivenName>Mitesh</GivenName><FamilyName>Meswani</FamilyName></AuthorName><Contact><Email>mitesh@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff18"><AuthorName DisplayOrder="Western"><GivenName>Laura</GivenName><FamilyName>Carrington</FamilyName></AuthorName><Contact><Email>lcarring@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff18"><AuthorName DisplayOrder="Western"><GivenName>Allan</GivenName><FamilyName>Snavely</FamilyName></AuthorName><Contact><Email>allans@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff19"><AuthorName DisplayOrder="Western"><GivenName>Mustafa</GivenName><GivenName>M.</GivenName><FamilyName>Tikir</FamilyName></AuthorName><Contact><Email>mustafa.m.tikir@gmail.com</Email></Contact></Author><Author AffiliationIDS="Aff20"><AuthorName DisplayOrder="Western"><GivenName>Stephen</GivenName><FamilyName>Poole</FamilyName></AuthorName><Contact><Email>spoole@ornl.gov</Email></Contact></Author><Affiliation ID="Aff18"><OrgName>San Diego Supercomputer Center</OrgName><OrgAddress><City>La Jolla</City><State>CA</State><Country>United States of America</Country></OrgAddress></Affiliation><Affiliation ID="Aff19"><OrgName>Google, Inc</OrgName><OrgAddress><City>Mountain View</City><State>CA</State><Country>United States of America</Country></OrgAddress></Affiliation><Affiliation ID="Aff20"><OrgName>Oak Ridge National Laboratory</OrgName><OrgAddress><City>Oak Ridge</City><State>TN</State><Country>United States of America</Country></OrgAddress></Affiliation></AuthorGroup><Abstract ID="Abs1" Language="En"><Heading>Abstract</Heading><Para>Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires <Emphasis Type="Italic">application signatures</Emphasis> - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a <Emphasis Type="Italic">machine characterization</Emphasis> of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.</Para></Abstract><KeywordGroup Language="En"><Heading>Keywords</Heading><Keyword>High Performance Computing</Keyword><Keyword>Dynamic Voltage Frequency Scaling</Keyword><Keyword>Benchmarking</Keyword><Keyword>Memory Latency</Keyword><Keyword>Energy Optimization</Keyword></KeywordGroup></ChapterHeader><NoBody></NoBody></Chapter></Part></Book></Series></Publisher></istex:document></istex:metadataXml><mods version="3.6"><titleInfo lang="en"><title>Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title></titleInfo><titleInfo type="alternative" contentType="CDATA" lang="en"><title>Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling</title></titleInfo><name type="personal"><namePart type="given">Michael</namePart><namePart type="given">A.</namePart><namePart type="family">Laurenzano</namePart><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation><affiliation>E-mail: michaell@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Mitesh</namePart><namePart type="family">Meswani</namePart><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation><affiliation>E-mail: mitesh@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Laura</namePart><namePart type="family">Carrington</namePart><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation><affiliation>E-mail: lcarring@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Allan</namePart><namePart type="family">Snavely</namePart><affiliation>San Diego Supercomputer Center, La Jolla, CA, United States of America</affiliation><affiliation>E-mail: allans@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Mustafa</namePart><namePart type="given">M.</namePart><namePart type="family">Tikir</namePart><affiliation>Google, Inc, Mountain View, CA, United States of America</affiliation><affiliation>E-mail: mustafa.m.tikir@gmail.com</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Stephen</namePart><namePart type="family">Poole</namePart><affiliation>Oak Ridge National Laboratory, Oak Ridge, TN, United States of America</affiliation><affiliation>E-mail: spoole@ornl.gov</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre type="conference" displayLabel="OriginalPaper"></genre><originInfo><publisher>Springer Berlin Heidelberg</publisher><place><placeTerm type="text">Berlin, Heidelberg</placeTerm></place><dateIssued encoding="w3cdtf">2011</dateIssued><copyrightDate encoding="w3cdtf">2011</copyrightDate></originInfo><language><languageTerm type="code" authority="rfc3066">en</languageTerm><languageTerm type="code" authority="iso639-2b">eng</languageTerm></language><physicalDescription><internetMediaType>text/html</internetMediaType></physicalDescription><abstract lang="en">Abstract: Over the life of a modern supercomputer, the energy cost of running the system can exceed the cost of the original hardware purchase. This has driven the community to attempt to understand and minimize energy costs wherever possible. Towards these ends, we present an automated, fine-grained approach to selecting per-loop processor clock frequencies. The clock frequency selection criteria is established through a combination of lightweight static analysis and runtime tracing that automatically acquires application signatures - characterizations of the patterns of execution of each loop in an application. This application characterization is matched with one of a series of benchmark loops, which have been run on the target system and probe it in various ways. These benchmarks form a covering set, a machine characterization of the expected power consumption and performance traits of the machine over the space of execution patterns and clock frequencies. The frequency that confers the optimal behavior in terms of power-delay product for the benchmark that most closely resembles each application loop is the one chosen for that loop. The set of tools that implement this scheme is fully automated, built on top of freely available open source software, and uses an inexpensive power measurement apparatus. We use these tools to show a measured, system-wide energy savings of up to 7.6% on an 8-core Intel Xeon E5530 and 10.6% on a 32-core AMD Opteron 8380 (a Sun X4600 Node) across a range of workloads.</abstract><relatedItem type="host"><titleInfo><title>Euro-Par 2011 Parallel Processing</title><subTitle>17th International Conference, Euro-Par 2011, Bordeaux, France, August 29 - September 2, 2011, Proceedings, Part I</subTitle></titleInfo><name type="personal"><namePart type="given">Emmanuel</namePart><namePart type="family">Jeannot</namePart><affiliation>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation><affiliation>E-mail: emmanuel.jeannot@inria.fr</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Raymond</namePart><namePart type="family">Namyst</namePart><affiliation>Equipe Runtime, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation><affiliation>E-mail: raymond.namyst@labri.fr</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Jean</namePart><namePart type="family">Roman</namePart><affiliation>Equipe HIEPACS, INRIA Bordeaux Sud-Ouest, 33405, Talence Cedex, France</affiliation><affiliation>E-mail: jean.roman@inria.fr</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><genre type="book-series" displayLabel="Proceedings"></genre><originInfo><copyrightDate encoding="w3cdtf">2011</copyrightDate><issuance>monographic</issuance></originInfo><subject><genre>Book-Subject-Collection</genre><topic authority="SpringerSubjectCodes" authorityURI="SUCO11645">Computer Science</topic></subject><subject><genre>Book-Subject-Group</genre><topic authority="SpringerSubjectCodes" authorityURI="I">Computer Science</topic><topic authority="SpringerSubjectCodes" authorityURI="I16013">Computation by Abstract Devices</topic><topic authority="SpringerSubjectCodes" authorityURI="I14010">Programming Techniques</topic><topic authority="SpringerSubjectCodes" authorityURI="I14037">Programming Languages, Compilers, Interpreters</topic><topic authority="SpringerSubjectCodes" authorityURI="I1701X">Numeric Computing</topic><topic authority="SpringerSubjectCodes" authorityURI="I13030">Special Purpose and Application-Based Systems</topic><topic authority="SpringerSubjectCodes" authorityURI="I14045">Operating Systems</topic></subject><identifier type="DOI">10.1007/978-3-642-23400-2</identifier><identifier type="ISBN">978-3-642-23399-9</identifier><identifier type="eISBN">978-3-642-23400-2</identifier><identifier type="ISSN">0302-9743</identifier><identifier type="eISSN">1611-3349</identifier><identifier type="BookTitleID">272698</identifier><identifier type="BookID">978-3-642-23400-2</identifier><identifier type="BookChapterCount">54</identifier><identifier type="BookVolumeNumber">6852</identifier><identifier type="BookSequenceNumber">6852</identifier><identifier type="PartChapterCount">7</identifier><part><date>2011</date><detail type="part"><title>Topic 2: Performance Prediction and Evaluation</title></detail><detail type="volume"><number>6852</number><caption>vol.</caption></detail><extent unit="pages"><start>79</start><end>90</end></extent></part><recordInfo><recordOrigin>Springer-Verlag GmbH Berlin Heidelberg, 2011</recordOrigin></recordInfo></relatedItem><relatedItem type="series"><titleInfo><title>Lecture Notes in Computer Science</title></titleInfo><name type="personal"><namePart type="given">David</namePart><namePart type="family">Hutchison</namePart><affiliation>Lancaster University, Lancaster, UK</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Takeo</namePart><namePart type="family">Kanade</namePart><affiliation>Carnegie Mellon University, Pittsburgh, PA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Josef</namePart><namePart type="family">Kittler</namePart><affiliation>University of Surrey, Guildford, UK</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Jon</namePart><namePart type="given">M.</namePart><namePart type="family">Kleinberg</namePart><affiliation>Cornell University, Ithaca, NY, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Friedemann</namePart><namePart type="family">Mattern</namePart><affiliation>ETH Zurich, Zurich, Switzerland</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">John</namePart><namePart type="given">C.</namePart><namePart type="family">Mitchell</namePart><affiliation>Stanford University, Stanford, CA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Moni</namePart><namePart type="family">Naor</namePart><affiliation>Weizmann Institute of Science, Rehovot, Israel</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Oscar</namePart><namePart type="family">Nierstrasz</namePart><affiliation>University of Bern, Bern, Switzerland</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">C.</namePart><namePart type="family">Pandu Rangan</namePart><affiliation>Indian Institute of Technology, Madras, India</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Bernhard</namePart><namePart type="family">Steffen</namePart><affiliation>University of Dortmund, Dortmund, Germany</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Madhu</namePart><namePart type="family">Sudan</namePart><affiliation>Massachusetts Institute of Technology, MA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Demetri</namePart><namePart type="family">Terzopoulos</namePart><affiliation>University of California, Los Angeles, CA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Doug</namePart><namePart type="family">Tygar</namePart><affiliation>University of California, Berkeley, CA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Moshe</namePart><namePart type="given">Y.</namePart><namePart type="family">Vardi</namePart><affiliation>Rice University, Houston, TX, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Gerhard</namePart><namePart type="family">Weikum</namePart><affiliation>Max-Planck Institute of Computer Science, Saarbrücken, Germany</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><originInfo><copyrightDate encoding="w3cdtf">2011</copyrightDate><issuance>serial</issuance></originInfo><identifier type="ISSN">0302-9743</identifier><identifier type="eISSN">1611-3349</identifier><identifier type="SeriesID">558</identifier><recordInfo><recordOrigin>Springer-Verlag GmbH Berlin Heidelberg, 2011</recordOrigin></recordInfo></relatedItem><identifier type="istex">85C771693C049D6774CFC213948CA9939456C56E</identifier><identifier type="DOI">10.1007/978-3-642-23400-2_9</identifier><identifier type="ChapterID">9</identifier><identifier type="ChapterID">Chap9</identifier><accessCondition type="use and reproduction" contentType="copyright">Springer-Verlag GmbH Berlin Heidelberg, 2011</accessCondition><recordInfo><recordContentSource>SPRINGER</recordContentSource><recordOrigin>Springer-Verlag Berlin Heidelberg, 2011</recordOrigin></recordInfo></mods></metadata><enrichments><json:item><type>multicat</type><uri>https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/enrichments/multicat</uri></json:item><istex:refBibTEI uri="https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/enrichments/refBib"><teiHeader></teiHeader><text><front></front><body></body><back><listBibl><biblStruct xml:id="b0"><analytic><title level="a" type="main">Cramming More Components onto Integrated Circuits</title><author><persName><forename type="first">G</forename><forename type="middle">E</forename><surname>Moore</surname></persName></author></analytic><monogr><title level="j">Electronics Magazine</title><imprint><date type="published" when="1965"></date></imprint></monogr></biblStruct><biblStruct xml:id="b1"><monogr><title level="m" type="main">Enhanced Intel SpeedStep Technology and Demand-Based Switching on Linux, http://software.intel.com/en-us/articles/enhanced- intel-speedstepr-technology-and-demand-based-switching-on-linux</title><author><persName><forename type="first">V</forename><surname>Pallipadi</surname></persName></author><imprint></imprint></monogr></biblStruct><biblStruct xml:id="b2"><analytic><title></title></analytic><monogr><title level="j">AMD PowerNow! Technology</title><imprint><biblScope unit="volume">5</biblScope></imprint></monogr></biblStruct><biblStruct xml:id="b3"><monogr><title level="m" type="main">STREAM: Sustainable Memory Bandwidth in High Performance Computers</title><author><persName><forename type="first">J</forename><forename type="middle">D</forename><surname>Mccalpin</surname></persName></author><imprint><date type="published" when="2000"></date></imprint></monogr></biblStruct><biblStruct xml:id="b4"><analytic><title level="a" type="main">PEBIL: Efficient Static Binary Instrumentation for Linux</title><author><persName><forename type="first">M</forename><forename type="middle">A</forename><surname>Laurenzano</surname></persName></author></analytic><monogr><title level="m">International Symposium on Performance Analysis of Systems and Software</title><imprint><date type="published" when="2010"></date></imprint></monogr></biblStruct><biblStruct xml:id="b5"><monogr><title></title><author><persName><forename type="first">Sdsc</forename><surname>San</surname></persName></author><author><persName><forename type="first">Diego</forename><forename type="middle">Supercomputer</forename><surname>Center</surname></persName></author><imprint><biblScope unit="page" from="5530" to="7"></biblScope></imprint></monogr></biblStruct><biblStruct xml:id="b6"><monogr><title></title><author><persName><forename type="first">Sun</forename><surname>Fire</surname></persName></author><author><persName><forename type="first">X4600</forename><surname>M2 Server</surname></persName></author><author><persName><surname>Architecture</surname></persName></author><imprint></imprint></monogr></biblStruct><biblStruct xml:id="b7"><analytic><title level="a" type="main">The AMD Opteron Processor for Multiprocessor Servers</title><author><persName><forename type="first">C</forename><forename type="middle">N</forename><surname>Keltcher</surname></persName></author></analytic><monogr><title level="m">International Symposium on Microarchitecture</title><imprint><date type="published" when="2003"></date></imprint></monogr></biblStruct><biblStruct xml:id="b8"><analytic><title level="a" type="main">The NAS Parallel Benchmarks</title><author><persName><forename type="first">D</forename><forename type="middle">H</forename><surname>Bailey</surname></persName></author></analytic><monogr><title level="j">International Journal of High Performance Computing Applications</title><imprint><date type="published" when="1991"></date></imprint></monogr></biblStruct><biblStruct xml:id="b9"><analytic><title level="a" type="main">Introduction to the HPC Challenge Benchmark Suite</title><author><persName><forename type="first">P</forename><surname>Luszczek</surname></persName></author></analytic><monogr><title level="m">International Conference on Supercomputing</title><imprint><date type="published" when="2005"></date></imprint></monogr></biblStruct><biblStruct xml:id="b10"><analytic><title level="a" type="main">Designing Scalable Synthetic Compact Applications for Benchmarking High Productivity Computing Systems</title><author><persName><forename type="first">D</forename><forename type="middle">A</forename><surname>Bader</surname></persName></author></analytic><monogr><title level="j">Cyberinfrastructure Technology Watch</title><imprint><date type="published" when="2006"></date></imprint></monogr></biblStruct><biblStruct xml:id="b11"><analytic><title level="a" type="main">Direct Numerical Simulation of Turbulent Combustion: Fundamental Insights Towards Predictive Models</title><author><persName><forename type="first">E</forename><forename type="middle">R</forename><surname>Hawkes</surname></persName></author></analytic><monogr><title level="j">Journal of Physics: Conference Series</title><imprint><date type="published" when="2005"></date></imprint></monogr></biblStruct><biblStruct xml:id="b12"><analytic><title level="a" type="main">Evaluation of Vertical Coordinate and Vertical Mixing Algorithms in the HYbrid-Coordinate Ocean Model (HYCOM)</title><author><persName><forename type="first">G</forename><forename type="middle">R</forename><surname>Halliwell</surname></persName></author></analytic><monogr><title level="j">Ocean Modelling</title><imprint><date type="published" when="2004"></date></imprint></monogr></biblStruct><biblStruct xml:id="b13"><analytic><title level="a" type="main">Feedback-based Dynamic Voltage and Frequency Scaling for Memory-bound Real-time Applications</title><author><persName><forename type="first">C</forename><surname>Poellabauer</surname></persName></author></analytic><monogr><title level="m">Real Time and Embedded Technology and Applications Symposium</title><imprint><date type="published" when="2005"></date></imprint></monogr></biblStruct><biblStruct xml:id="b14"><analytic><title level="a" type="main">Dynamic Voltage and Frequency Scaling Based on Workload Decomposition</title><author><persName><forename type="first">K</forename><surname>Choi</surname></persName></author></analytic><monogr><title level="m">International Symposium on Low Power Electronics and Design</title><imprint><date type="published" when="2004"></date></imprint></monogr></biblStruct><biblStruct xml:id="b15"><analytic><title level="a" type="main">Application-aware Power Management</title><author><persName><forename type="first">K</forename><surname>Rajamani</surname></persName></author></analytic><monogr><title level="m">Symposium on Workload Characterization</title><imprint><date type="published" when="2007"></date></imprint></monogr></biblStruct><biblStruct xml:id="b16"><analytic><title level="a" type="main">An Analysis of Efficient Multi-core Global Power Management Policies: Maximizing Performance for a Given Power Budget</title><author><persName><forename type="first">C</forename><surname>Isci</surname></persName></author></analytic><monogr><title level="m">International Symposium on Microarchitecture</title><imprint><date type="published" when="2006"></date></imprint></monogr></biblStruct><biblStruct xml:id="b17"><analytic><title level="a" type="main">Operating System Modifications for Task-Based Speed and Voltage</title><author><persName><forename type="first">J</forename><forename type="middle">R</forename><surname>Lorch</surname></persName></author><author><persName><forename type="first">A</forename><forename type="middle">J</forename><surname>Smith</surname></persName></author></analytic><monogr><title level="m">International Conference on Mobile Systems, Applications and Services</title><imprint><date type="published" when="2003"></date></imprint></monogr></biblStruct><biblStruct xml:id="b18"><analytic><title level="a" type="main">Just-in-time Dynamic Voltage Scaling: Exploiting Inter-node Slack to Save Energy in MPI Programs</title><author><persName><forename type="first">V</forename><forename type="middle">W</forename><surname>Freeh</surname></persName></author></analytic><monogr><title level="j">Journal of Parallel and Distributed Computing</title><imprint><date type="published" when="2008"></date></imprint></monogr></biblStruct><biblStruct xml:id="b19"><analytic><title level="a" type="main">Emprical Study on Reducing Energy of Parallel Programs using Slack Reclamation by DVFS in a Power-scalable High Performance Cluster</title><author><persName><forename type="first">H</forename><surname>Kimura</surname></persName></author></analytic><monogr><title level="m">International Conference on Cluster Computing</title><imprint><date type="published" when="2007"></date></imprint></monogr></biblStruct><biblStruct xml:id="b20"><analytic><title level="a" type="main">Improvement of Power-performance Efficiency for High-end Computing</title><author><persName><forename type="first">R</forename><surname>Ge</surname></persName></author></analytic><monogr><title level="m">Parallel and Distributed Processing Symposium</title><imprint><date type="published" when="2005"></date></imprint></monogr></biblStruct><biblStruct xml:id="b21"><analytic><title level="a" type="main">Using Multiple Energy Gears in MPI programs on a Power-scalable Cluster</title><author><persName><forename type="first">V</forename><forename type="middle">W</forename><surname>Freeh</surname></persName></author><author><persName><forename type="first">D</forename><forename type="middle">K</forename><surname>Lowenthal</surname></persName></author></analytic><monogr><title level="m">Symposium on Principles and Practice of Parallel Programming</title><imprint><date type="published" when="2005"></date></imprint></monogr></biblStruct></listBibl></back></text></istex:refBibTEI><json:item><type>refBibs</type><uri>https://api.istex.fr/document/85C771693C049D6774CFC213948CA9939456C56E/enrichments/refBibs</uri></json:item></enrichments></istex></record>Pour manipuler ce document sous Unix (Dilib)
EXPLOR_STEP=$WICRI_ROOT/Ticri/CIDE/explor/CyberinfraV1/Data/Istex/Corpus
HfdSelect -h $EXPLOR_STEP/biblio.hfd -nk 000383 | SxmlIndent | more
Ou
HfdSelect -h $EXPLOR_AREA/Data/Istex/Corpus/biblio.hfd -nk 000383 | SxmlIndent | more
Pour mettre un lien sur cette page dans le réseau Wicri
{{Explor lien
|wiki= Ticri/CIDE
|area= CyberinfraV1
|flux= Istex
|étape= Corpus
|type= RBID
|clé= ISTEX:85C771693C049D6774CFC213948CA9939456C56E
|texte= Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
}}
| This area was generated with Dilib version V0.6.25. |  |