D'un formalisme à l'autre : entre TIOSM et SDL
Identifieur interne : 005956 ( Hal/Curation ); précédent : 005955; suivant : 005957D'un formalisme à l'autre : entre TIOSM et SDL
Auteurs : Laurent Kaiser [France] ; Françoise Simonot-Lion [France]Source :
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Abstract
Dans cet article, nous proposons une méthode pour traduire formellement un système décrit dans le formalisme d'une sous-classe des automates temporisés, appellée TIOSM (Timed Input Output State Machine) dans un modèle écrit en SDL (Specification and description Language). La traduction est illustrée sur un exemple simple. Nous montrons par ailleurs en quoi le modèle est dégradé dans cette traduction en raison d'une représentation du temps différente pour chaque formalisme.
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Hal:inria-00100723Le document en format XML
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<front><div type="abstract" xml:lang="fr">Dans cet article, nous proposons une méthode pour traduire formellement un système décrit dans le formalisme d'une sous-classe des automates temporisés, appellée TIOSM (Timed Input Output State Machine) dans un modèle écrit en SDL (Specification and description Language). La traduction est illustrée sur un exemple simple. Nous montrons par ailleurs en quoi le modèle est dégradé dans cette traduction en raison d'une représentation du temps différente pour chaque formalisme.</div>
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<sourceDesc><biblStruct><analytic><title xml:lang="fr">D'un formalisme à l'autre : entre TIOSM et SDL</title>
<author role="aut"><persName><forename type="first">Laurent</forename>
<surname>Kaiser</surname>
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<author role="aut"><persName><forename type="first">Françoise</forename>
<surname>Simonot-Lion</surname>
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<email>Francoise.Simonot-Lion@ensem.inpl-nancy.fr</email>
<idno type="halAuthorId">131964</idno>
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<meeting><title>10th Conference on Real Time and Embedded Systems</title>
<date type="start">2002-03</date>
<settlement>Paris/France</settlement>
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<imprint><biblScope unit="pp">12 p</biblScope>
<date type="datePub">2002-03</date>
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<textClass><keywords scheme="author"><term xml:lang="fr">formal description techniques</term>
<term xml:lang="fr">formal verification</term>
<term xml:lang="fr">timed automata</term>
<term xml:lang="fr">vérification formelle</term>
<term xml:lang="fr">automates temporisés</term>
<term xml:lang="fr">techniques de description formelle</term>
<term xml:lang="fr">validation</term>
</keywords>
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<abstract xml:lang="fr">Dans cet article, nous proposons une méthode pour traduire formellement un système décrit dans le formalisme d'une sous-classe des automates temporisés, appellée TIOSM (Timed Input Output State Machine) dans un modèle écrit en SDL (Specification and description Language). La traduction est illustrée sur un exemple simple. Nous montrons par ailleurs en quoi le modèle est dégradé dans cette traduction en raison d'une représentation du temps différente pour chaque formalisme.</abstract>
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