Evolvable platform for array processing : a one-chip approach
Identifieur interne : 002495 ( Crin/Corpus ); précédent : 002494; suivant : 002496Evolvable platform for array processing : a one-chip approach
Auteurs : Bernard Girau ; Pierre Marchal ; Pascal Nussbaum ; Arnaud Tisserand ; Hector Fabio RestrepoSource :
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The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array (FPPA). The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principe, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" wicri:score="224">Evolvable platform for array processing : a one-chip approach</title></titleStmt><publicationStmt><idno type="RBID">CRIN:girau99v</idno><date when="1999" year="1999">1999</date><idno type="wicri:Area/Crin/Corpus">002495</idno></publicationStmt><sourceDesc><biblStruct><analytic><title xml:lang="en">Evolvable platform for array processing : a one-chip approach</title><author><name sortKey="Girau, Bernard" sort="Girau, Bernard" uniqKey="Girau B" first="Bernard" last="Girau">Bernard Girau</name></author><author><name sortKey="Marchal, Pierre" sort="Marchal, Pierre" uniqKey="Marchal P" first="Pierre" last="Marchal">Pierre Marchal</name></author><author><name sortKey="Nussbaum, Pascal" sort="Nussbaum, Pascal" uniqKey="Nussbaum P" first="Pascal" last="Nussbaum">Pascal Nussbaum</name></author><author><name sortKey="Tisserand, Arnaud" sort="Tisserand, Arnaud" uniqKey="Tisserand A" first="Arnaud" last="Tisserand">Arnaud Tisserand</name></author><author><name sortKey="Restrepo, Hector Fabio" sort="Restrepo, Hector Fabio" uniqKey="Restrepo H" first="Hector Fabio" last="Restrepo">Hector Fabio Restrepo</name></author></analytic></biblStruct></sourceDesc></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>processor array</term><term>programmable hardware</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en" wicri:score="1653">The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array (FPPA). The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principe, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.</div></front></TEI><BibTex type="inproceedings"><ref>girau99v</ref><crinnumber>99-R-026</crinnumber><category>3</category><equipe>CORTEX</equipe><author><e>Girau, Bernard</e><e>Marchal, Pierre</e><e>Nussbaum, Pascal</e><e>Tisserand, Arnaud</e><e>Restrepo, Hector Fabio</e></author><title>Evolvable platform for array processing : a one-chip approach</title><booktitle>{MicroNeuro, Granada, Spain}</booktitle><year>1999</year><month>Apr</month><keywords><e>programmable hardware</e><e>processor array</e></keywords><abstract>The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array (FPPA). The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principe, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.</abstract></BibTex></record>Pour manipuler ce document sous Unix (Dilib)
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