PSnAP: Accurate Synthetic Address Streams through Memory Profiles
Identifieur interne : 000661 ( Istex/Corpus ); précédent : 000660; suivant : 000662PSnAP: Accurate Synthetic Address Streams through Memory Profiles
Auteurs : Mills Olschanowsky ; M. Tikir ; Laura Carrington ; Allan SnavelySource :
- Lecture Notes in Computer Science [ 0302-9743 ] ; 2010.
Abstract
Abstract: Memory address traces are an important information source; they drive memory simulations for performance modeling, systems design and application tuning. For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. The combination of small profile sizes and high similarity to original traces makes our technique uniquely applicable to performance modeling and trace driven simulation of large-scale parallel scientific applications.
Url:
DOI: 10.1007/978-3-642-13374-9_24
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For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. 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For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. 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University</OrgName><OrgAddress><City>Pittsburgh</City><State>PA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff3"><OrgName>University of Surrey</OrgName><OrgAddress><City>Guildford</City><Country>UK</Country></OrgAddress></Affiliation><Affiliation ID="Aff4"><OrgName>Cornell University</OrgName><OrgAddress><City>Ithaca</City><State>NY</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff5"><OrgName>ETH Zurich</OrgName><OrgAddress><City>Zurich</City><Country>Switzerland</Country></OrgAddress></Affiliation><Affiliation ID="Aff6"><OrgName>Stanford University</OrgName><OrgAddress><City>Stanford</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff7"><OrgName>Weizmann Institute of Science</OrgName><OrgAddress><City>Rehovot</City><Country>Israel</Country></OrgAddress></Affiliation><Affiliation ID="Aff8"><OrgName>University of Bern</OrgName><OrgAddress><City>Bern</City><Country>Switzerland</Country></OrgAddress></Affiliation><Affiliation ID="Aff9"><OrgName>Indian Institute of Technology</OrgName><OrgAddress><City>Madras</City><Country>India</Country></OrgAddress></Affiliation><Affiliation ID="Aff10"><OrgName>University of Dortmund</OrgName><OrgAddress><City>Dortmund</City><Country>Germany</Country></OrgAddress></Affiliation><Affiliation ID="Aff11"><OrgName>Massachusetts Institute of Technology</OrgName><OrgAddress><State>MA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff12"><OrgName>University of California</OrgName><OrgAddress><City>Los Angeles</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff13"><OrgName>University of California</OrgName><OrgAddress><City>Berkeley</City><State>CA</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff14"><OrgName>Rice University</OrgName><OrgAddress><City>Houston</City><State>TX</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff15"><OrgName>Max-Planck Institute of Computer Science</OrgName><OrgAddress><City>Saarbrücken</City><Country>Germany</Country></OrgAddress></Affiliation></EditorGroup></SeriesHeader><Book Language="En"><BookInfo BookProductType="Proceedings" ContainsESM="No" Language="En" MediaType="eBook" NumberingDepth="2" NumberingStyle="ContentOnly" OutputMedium="All" TocLevels="0"><BookID>978-3-642-13374-9</BookID><BookTitle>Languages and Compilers for Parallel Computing</BookTitle><BookSubTitle>22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers</BookSubTitle><BookVolumeNumber>5898</BookVolumeNumber><BookSequenceNumber>5898</BookSequenceNumber><BookDOI>10.1007/978-3-642-13374-9</BookDOI><BookTitleID>211616</BookTitleID><BookPrintISBN>978-3-642-13373-2</BookPrintISBN><BookElectronicISBN>978-3-642-13374-9</BookElectronicISBN><BookChapterCount>30</BookChapterCount><BookCopyright><CopyrightHolderName>Springer-Verlag Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2010</CopyrightYear></BookCopyright><BookSubjectGroup><BookSubject Code="I" Type="Primary">Computer Science</BookSubject><BookSubject Code="I14037" Priority="1" Type="Secondary">Programming Languages, Compilers, Interpreters</BookSubject><BookSubject Code="I14010" Priority="2" Type="Secondary">Programming Techniques</BookSubject><BookSubject Code="I15017" Priority="3" Type="Secondary">Data Structures</BookSubject><BookSubject Code="I21009" Priority="4" Type="Secondary">Computing Methodologies</BookSubject><BookSubject Code="I18016" Priority="5" Type="Secondary">Models and Principles</BookSubject><BookSubject Code="I13022" Priority="6" Type="Secondary">Computer Communication Networks</BookSubject><SubjectCollection Code="SUCO11645">Computer Science</SubjectCollection></BookSubjectGroup><BookContext><SeriesID>558</SeriesID></BookContext></BookInfo><BookHeader><EditorGroup><Editor AffiliationIDS="Aff16"><EditorName DisplayOrder="Western"><GivenName>Guang</GivenName><GivenName>R.</GivenName><FamilyName>Gao</FamilyName></EditorName><Contact><Email>ggao@capsl.udel.edu</Email></Contact></Editor><Editor AffiliationIDS="Aff17"><EditorName DisplayOrder="Western"><GivenName>Lori</GivenName><GivenName>L.</GivenName><FamilyName>Pollock</FamilyName></EditorName><Contact><Email>pollock@cis.udel.edu</Email></Contact></Editor><Editor AffiliationIDS="Aff17"><EditorName DisplayOrder="Western"><GivenName>John</GivenName><FamilyName>Cavazos</FamilyName></EditorName><Contact><Email>cavazos@cis.udel.edu</Email></Contact></Editor><Editor AffiliationIDS="Aff16"><EditorName DisplayOrder="Western"><GivenName>Xiaoming</GivenName><FamilyName>Li</FamilyName></EditorName><Contact><Email>xli@ece.udel.edu</Email></Contact></Editor><Affiliation ID="Aff16"><OrgDivision>Department of Electrical and Computer Engineering</OrgDivision><OrgName>University of Delaware</OrgName><OrgAddress><Postcode>19716</Postcode><City>Newark</City><State>DE</State><Country>USA</Country></OrgAddress></Affiliation><Affiliation ID="Aff17"><OrgDivision>Department of Computer and Information Sciences</OrgDivision><OrgName>University of Delaware</OrgName><OrgAddress><Postcode>19716</Postcode><City>Newark</City><State>DE</State><Country>USA</Country></OrgAddress></Affiliation></EditorGroup></BookHeader><Chapter ID="Chap24" Language="En"><ChapterInfo ChapterType="OriginalPaper" ContainsESM="No" NumberingDepth="2" NumberingStyle="ContentOnly" TocLevels="0"><ChapterID>24</ChapterID><ChapterDOI>10.1007/978-3-642-13374-9_24</ChapterDOI><ChapterSequenceNumber>24</ChapterSequenceNumber><ChapterTitle Language="En">PSnAP: Accurate Synthetic Address Streams through Memory Profiles</ChapterTitle><ChapterFirstPage>353</ChapterFirstPage><ChapterLastPage>367</ChapterLastPage><ChapterCopyright><CopyrightHolderName>Springer-Verlag Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2010</CopyrightYear></ChapterCopyright><ChapterGrants Type="Regular"><MetadataGrant Grant="OpenAccess"></MetadataGrant><AbstractGrant Grant="OpenAccess"></AbstractGrant><BodyPDFGrant Grant="Restricted"></BodyPDFGrant><BodyHTMLGrant Grant="Restricted"></BodyHTMLGrant><BibliographyGrant Grant="Restricted"></BibliographyGrant><ESMGrant Grant="Restricted"></ESMGrant></ChapterGrants><ChapterContext><SeriesID>558</SeriesID><BookID>978-3-642-13374-9</BookID><BookTitle>Languages and Compilers for Parallel Computing</BookTitle></ChapterContext></ChapterInfo><ChapterHeader><AuthorGroup><Author AffiliationIDS="Aff18"><AuthorName DisplayOrder="Western"><GivenName>Catherine</GivenName><GivenName>Mills</GivenName><FamilyName>Olschanowsky</FamilyName></AuthorName><Contact><Email>crmills@cs.ucsd.edu</Email></Contact></Author><Author AffiliationIDS="Aff19"><AuthorName DisplayOrder="Western"><GivenName>Mustafa</GivenName><GivenName>M.</GivenName><FamilyName>Tikir</FamilyName></AuthorName><Contact><Email>mtikir@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff19"><AuthorName DisplayOrder="Western"><GivenName>Laura</GivenName><FamilyName>Carrington</FamilyName></AuthorName><Contact><Email>lcarring@sdsc.edu</Email></Contact></Author><Author AffiliationIDS="Aff18 Aff19"><AuthorName DisplayOrder="Western"><GivenName>Allan</GivenName><FamilyName>Snavely</FamilyName></AuthorName><Contact><Email>allans@cs.ucsd.edu</Email><Email>allans@sdsc.edu</Email></Contact></Author><Affiliation ID="Aff18"><OrgDivision>Department of Computer Science and Engineering</OrgDivision><OrgName>University of California at San Diego</OrgName><OrgAddress><Country> </Country></OrgAddress></Affiliation><Affiliation ID="Aff19"><OrgName>San Diego Supercomputer Center</OrgName><OrgAddress><Country> </Country></OrgAddress></Affiliation></AuthorGroup><Abstract ID="Abs1" Language="En"><Heading>Abstract</Heading><Para>Memory address traces are an important information source; they drive memory simulations for performance modeling, systems design and application tuning. For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. The combination of small profile sizes and high similarity to original traces makes our technique uniquely applicable to performance modeling and trace driven simulation of large-scale parallel scientific applications.</Para></Abstract></ChapterHeader><NoBody></NoBody></Chapter></Book></Series></Publisher></istex:document></istex:metadataXml><mods version="3.6"><titleInfo lang="en"><title>PSnAP: Accurate Synthetic Address Streams through Memory Profiles</title></titleInfo><titleInfo type="alternative" contentType="CDATA" lang="en"><title>PSnAP: Accurate Synthetic Address Streams through Memory Profiles</title></titleInfo><name type="personal"><namePart type="given">Catherine</namePart><namePart type="given">Mills</namePart><namePart type="family">Olschanowsky</namePart><affiliation>Department of Computer Science and Engineering, University of California at San Diego</affiliation><affiliation>E-mail: crmills@cs.ucsd.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Mustafa</namePart><namePart type="given">M.</namePart><namePart type="family">Tikir</namePart><affiliation>San Diego Supercomputer Center</affiliation><affiliation>E-mail: mtikir@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Laura</namePart><namePart type="family">Carrington</namePart><affiliation>San Diego Supercomputer Center</affiliation><affiliation>E-mail: lcarring@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Allan</namePart><namePart type="family">Snavely</namePart><affiliation>Department of Computer Science and Engineering, University of California at San Diego</affiliation><affiliation>San Diego Supercomputer Center</affiliation><affiliation>E-mail: allans@cs.ucsd.edu</affiliation><affiliation>E-mail: allans@sdsc.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre type="conference" displayLabel="OriginalPaper"></genre><originInfo><publisher>Springer Berlin Heidelberg</publisher><place><placeTerm type="text">Berlin, Heidelberg</placeTerm></place><dateIssued encoding="w3cdtf">2010</dateIssued><copyrightDate encoding="w3cdtf">2010</copyrightDate></originInfo><language><languageTerm type="code" authority="rfc3066">en</languageTerm><languageTerm type="code" authority="iso639-2b">eng</languageTerm></language><physicalDescription><internetMediaType>text/html</internetMediaType></physicalDescription><abstract lang="en">Abstract: Memory address traces are an important information source; they drive memory simulations for performance modeling, systems design and application tuning. For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. The combination of small profile sizes and high similarity to original traces makes our technique uniquely applicable to performance modeling and trace driven simulation of large-scale parallel scientific applications.</abstract><relatedItem type="host"><titleInfo><title>Languages and Compilers for Parallel Computing</title><subTitle>22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers</subTitle></titleInfo><name type="personal"><namePart type="given">Guang</namePart><namePart type="given">R.</namePart><namePart type="family">Gao</namePart><affiliation>Department of Electrical and Computer Engineering, University of Delaware, 19716, Newark, DE, USA</affiliation><affiliation>E-mail: ggao@capsl.udel.edu</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Lori</namePart><namePart type="given">L.</namePart><namePart type="family">Pollock</namePart><affiliation>Department of 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type="family">Hutchison</namePart><affiliation>Lancaster University, Lancaster, UK</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Takeo</namePart><namePart type="family">Kanade</namePart><affiliation>Carnegie Mellon University, Pittsburgh, PA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Josef</namePart><namePart type="family">Kittler</namePart><affiliation>University of Surrey, Guildford, UK</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Jon</namePart><namePart type="given">M.</namePart><namePart type="family">Kleinberg</namePart><affiliation>Cornell University, Ithaca, NY, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Friedemann</namePart><namePart type="family">Mattern</namePart><affiliation>ETH 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India</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Bernhard</namePart><namePart type="family">Steffen</namePart><affiliation>University of Dortmund, Dortmund, Germany</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Madhu</namePart><namePart type="family">Sudan</namePart><affiliation>Massachusetts Institute of Technology, MA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Demetri</namePart><namePart type="family">Terzopoulos</namePart><affiliation>University of California, Los Angeles, CA, USA</affiliation><role><roleTerm type="text">editor</roleTerm></role></name><name type="personal"><namePart type="given">Doug</namePart><namePart type="family">Tygar</namePart><affiliation>University of California, Berkeley, CA, USA</affiliation><role><roleTerm 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