SrasV1, Hal, Curation, bibRecord, 000126

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Identifieur interne : 000126 ( Hal/Curation ); précédent : 000125; suivant : 000127

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Auteurs : R. Silveira Feitoza [France] ; Manuel J. Barragan [France] ; D. Dzahini [France] ; S. Mir [France]

Source :

IEEE Transactions on Device and Materials Reliability [ 1530-4388 ] ; 2019.

RBID : Hal:hal-01989117

Abstract

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution Incremental Sigma-Delta converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.

Url:

https://hal.archives-ouvertes.fr/hal-01989117

DOI: 10.1109/TDMR.2019.2891298

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Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

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