Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain
Identifieur interne : 000C58 ( Main/Corpus ); précédent : 000C57; suivant : 000C59Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain
Auteurs : Heinrich Wolf ; Horst Gieser ; Wolfgang StadlerSource :
- Microelectronics Reliability [ 0026-2714 ] ; 1999.
Abstract
The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.
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DOI: 10.1016/S0026-2714(99)00074-8
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<record><TEI wicri:istexFullTextTei="biblStruct"><teiHeader><fileDesc><titleStmt><title>Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title><author><name sortKey="Wolf, Heinrich" sort="Wolf, Heinrich" uniqKey="Wolf H" first="Heinrich" last="Wolf">Heinrich Wolf</name><affiliation><mods:affiliation>E-mail: wolf@ift.fhg.de</mods:affiliation></affiliation><affiliation><mods:affiliation>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</mods:affiliation></affiliation></author><author><name sortKey="Gieser, Horst" sort="Gieser, Horst" uniqKey="Gieser H" first="Horst" last="Gieser">Horst Gieser</name><affiliation><mods:affiliation>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</mods:affiliation></affiliation></author><author><name sortKey="Stadler, Wolfgang" sort="Stadler, Wolfgang" uniqKey="Stadler W" first="Wolfgang" last="Stadler">Wolfgang Stadler</name><affiliation><mods:affiliation>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</mods:affiliation></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:37DBA566093327825538A3415119203C1D7BC3A3</idno><date when="1999" year="1999">1999</date><idno type="doi">10.1016/S0026-2714(99)00074-8</idno><idno type="url">https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/fulltext/pdf</idno><idno type="wicri:Area/Main/Corpus">000C58</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a">Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title><author><name sortKey="Wolf, Heinrich" sort="Wolf, Heinrich" uniqKey="Wolf H" first="Heinrich" last="Wolf">Heinrich Wolf</name><affiliation><mods:affiliation>E-mail: wolf@ift.fhg.de</mods:affiliation></affiliation><affiliation><mods:affiliation>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</mods:affiliation></affiliation></author><author><name sortKey="Gieser, Horst" sort="Gieser, Horst" uniqKey="Gieser H" first="Horst" last="Gieser">Horst Gieser</name><affiliation><mods:affiliation>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</mods:affiliation></affiliation></author><author><name sortKey="Stadler, Wolfgang" sort="Stadler, Wolfgang" uniqKey="Stadler W" first="Wolfgang" last="Stadler">Wolfgang Stadler</name><affiliation><mods:affiliation>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</mods:affiliation></affiliation></author></analytic><monogr></monogr><series><title level="j">Microelectronics Reliability</title><title level="j" type="abbrev">MR</title><idno type="ISSN">0026-2714</idno><imprint><publisher>ELSEVIER</publisher><date type="published" when="1999">1999</date><biblScope unit="volume">39</biblScope><biblScope unit="issue">11</biblScope><biblScope unit="page" from="1541">1541</biblScope><biblScope unit="page" to="1549">1549</biblScope></imprint><idno type="ISSN">0026-2714</idno></series><idno type="istex">37DBA566093327825538A3415119203C1D7BC3A3</idno><idno type="DOI">10.1016/S0026-2714(99)00074-8</idno><idno type="PII">S0026-2714(99)00074-8</idno></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">0026-2714</idno></seriesStmt></fileDesc><profileDesc><textClass></textClass><langUsage><language ident="en">en</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.</div></front></TEI><istex><corpusName>elsevier</corpusName><author><json:item><name>Heinrich Wolf</name><affiliations><json:string>E-mail: wolf@ift.fhg.de</json:string><json:string>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</json:string></affiliations></json:item><json:item><name>Horst Gieser</name><affiliations><json:string>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</json:string></affiliations></json:item><json:item><name>Wolfgang Stadler</name><affiliations><json:string>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</json:string></affiliations></json:item></author><subject><json:item><lang><json:string>eng</json:string></lang><value>ESD</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>HBM</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Compact simulation</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Protection structure</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Gate coupling</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Bipolar transistor model</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>High current characteristic</value></json:item></subject><language><json:string>eng</json:string></language><abstract>The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.</abstract><qualityIndicators><score>5.133</score><pdfVersion>1.2</pdfVersion><pdfPageSize>595 x 792 pts</pdfPageSize><refBibsNative>true</refBibsNative><keywordCount>7</keywordCount><abstractCharCount>503</abstractCharCount><pdfWordCount>4257</pdfWordCount><pdfCharCount>25156</pdfCharCount><pdfPageCount>9</pdfPageCount><abstractWordCount>73</abstractWordCount></qualityIndicators><title>Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title><pii><json:string>S0026-2714(99)00074-8</json:string></pii><genre><json:string>research-article</json:string></genre><host><volume>39</volume><pii><json:string>S0026-2714(00)X0052-2</json:string></pii><pages><last>1549</last><first>1541</first></pages><issn><json:string>0026-2714</json:string></issn><issue>11</issue><genre></genre><language><json:string>unknown</json:string></language><title>Microelectronics Reliability</title><publicationDate>1999</publicationDate></host><categories><wos><json:string>ENGINEERING, ELECTRICAL & ELECTRONIC</json:string><json:string>PHYSICS, APPLIED</json:string><json:string>NANOSCIENCE & NANOTECHNOLOGY</json:string></wos></categories><publicationDate>1999</publicationDate><copyrightDate>1999</copyrightDate><doi><json:string>10.1016/S0026-2714(99)00074-8</json:string></doi><id>37DBA566093327825538A3415119203C1D7BC3A3</id><fulltext><json:item><original>true</original><mimetype>application/pdf</mimetype><extension>pdf</extension><uri>https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/fulltext/pdf</uri></json:item><json:item><original>false</original><mimetype>application/zip</mimetype><extension>zip</extension><uri>https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/fulltext/zip</uri></json:item><istex:fulltextTEI uri="https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/fulltext/tei"><teiHeader><fileDesc><titleStmt><title level="a">Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title></titleStmt><publicationStmt><authority>ISTEX</authority><publisher>ELSEVIER</publisher><availability><p>ELSEVIER</p></availability><date>1999</date></publicationStmt><notesStmt><note type="content">Fig. 1: The compact bipolar model is attached to a standard MOS model. The gate node influences the trigger behavior of the transistor. The whole structure forms a subcircuit ESD NMOS.</note><note type="content">Fig. 2: Equivalent circuit of the used compact model. The virtual gate node potential influences the avalanche current source Iava.</note><note type="content">Fig. 3: Schematic cross-section of the investigated NMOS protection transistor together with the parasitic bipolar transistor. We investigated several layout variations and compared them to the simulated data.</note><note type="content">Fig. 4: Comparison of the measured high current characteristic of the reference transistor with the simulated data computed with a constant current gain. The differential high current resistance is influenced in the model only by the collector resistor rc. This leads to a deviation of the simulation from the measurement at higher currents.</note><note type="content">Fig. 5: Comparison of the measured multiplication factor with the Miller-formula and a modified Miller function, which is implemented into the transistor model in order to improve the correlation with the measurement at lower device voltages.</note><note type="content">Fig. 6: Measured current gain of the investigated transistor as function of the drain current. For currents higher than 0.2 A, the gain decreases stronger.</note><note type="content">Fig. 7: Simulation of the current dependent gain for different proportionality constants cβ, influencing the decay of β and thus the differential high current resistance of the device. For the simulations we applied a cβ=1.43 A−1.</note><note type="content">Fig. 8: Comparison of the measured high current characteristic of the reference transistor with the simulated data computed with a stress current dependent current gain. The accuracy is significantly increased as compared to Fig. 4.</note><note type="content">Fig. 9: TLP characteristics of three devices with different high currents normalized to their gate width. The decreasing current density with increasing gate width indicates a inhomogenous current distribution.</note><note type="content">Fig. 10: Comparison of TLP measurements with compact simulation with variation of the gate width. The simulation correlates well with the measurement if an inhomogenous current distribution is taken into account.</note><note type="content">Fig. 11: Comparison of TLP measurements with compact simulation with variation of the gate length. The simulation again, correlates well with the measurement.</note><note type="content">Fig. 12: Comparison of TLP measurements with compact simulation with variation of the drain contact/gate spacing aD.</note><note type="content">Fig. 13: Transfer characteristics of the investigated NMOS protection transistor for different drain voltages. The MOS current influences the avalanche current of the parasitic bipolar transistor.</note><note type="content">Fig. 14: IV-characteristic of the bipolar model (without attached MOS model) for several gate voltages Vgs at the virtual gate node.</note><note type="content">Fig. 15: Comparison of the measured DC output characteristic for a gate voltage Vgs=1.5 V in comparison with the simulation. For the simulation, we extended a Berkeley Spice level 1 MOST with the bipolar transistor.</note><note type="content">Fig. 16: Simulation of the drain and gate potential for different coupling capacitances. The trigger voltage does not automatically decrease if a capacitance is introduced between drain and gate. For the simulation we applied a TLP pulse with 5 ns rise time.</note></notesStmt><sourceDesc><biblStruct type="inbook"><analytic><title level="a">Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title><author><persName><forename type="first">Heinrich</forename><surname>Wolf</surname></persName><email>wolf@ift.fhg.de</email><note type="correspondence"><p>Corresponding author. Tel.: +49-89-54759-031; fax: +49-89-54759-475</p></note><affiliation>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</affiliation></author><author><persName><forename type="first">Horst</forename><surname>Gieser</surname></persName><affiliation>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</affiliation></author><author><persName><forename type="first">Wolfgang</forename><surname>Stadler</surname></persName><affiliation>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</affiliation></author></analytic><monogr><title level="j">Microelectronics Reliability</title><title level="j" type="abbrev">MR</title><idno type="pISSN">0026-2714</idno><idno type="PII">S0026-2714(00)X0052-2</idno><imprint><publisher>ELSEVIER</publisher><date type="published" when="1999"></date><biblScope unit="volume">39</biblScope><biblScope unit="issue">11</biblScope><biblScope unit="page" from="1541">1541</biblScope><biblScope unit="page" to="1549">1549</biblScope></imprint></monogr><idno type="istex">37DBA566093327825538A3415119203C1D7BC3A3</idno><idno type="DOI">10.1016/S0026-2714(99)00074-8</idno><idno type="PII">S0026-2714(99)00074-8</idno></biblStruct></sourceDesc></fileDesc><profileDesc><creation><date>1999</date></creation><langUsage><language ident="en">en</language></langUsage><abstract xml:lang="en"><p>The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.</p></abstract><textClass><keywords scheme="keyword"><list><head>Keywords</head><item><term>ESD</term></item><item><term>HBM</term></item><item><term>Compact simulation</term></item><item><term>Protection structure</term></item><item><term>Gate coupling</term></item><item><term>Bipolar transistor model</term></item><item><term>High current characteristic</term></item></list></keywords></textClass></profileDesc><revisionDesc><change when="1999-05-30">Received</change><change when="1999">Published</change></revisionDesc></teiHeader></istex:fulltextTEI><json:item><original>false</original><mimetype>text/plain</mimetype><extension>txt</extension><uri>https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/fulltext/txt</uri></json:item></fulltext><metadata><istex:metadataXml wicri:clean="Elsevier, elements deleted: ce:floats; body; tail"><istex:xmlDeclaration>version="1.0" encoding="utf-8"</istex:xmlDeclaration><istex:docType PUBLIC="-//ES//DTD journal article DTD version 4.5.2//EN//XML" URI="art452.dtd" name="istex:docType"><istex:entity SYSTEM="gr1" NDATA="IMAGE" name="gr1"></istex:entity><istex:entity SYSTEM="gr2" NDATA="IMAGE" name="gr2"></istex:entity><istex:entity SYSTEM="gr3" NDATA="IMAGE" name="gr3"></istex:entity><istex:entity SYSTEM="gr4" NDATA="IMAGE" name="gr4"></istex:entity><istex:entity SYSTEM="gr5" NDATA="IMAGE" name="gr5"></istex:entity><istex:entity SYSTEM="gr6" NDATA="IMAGE" name="gr6"></istex:entity><istex:entity SYSTEM="gr7" NDATA="IMAGE" name="gr7"></istex:entity><istex:entity SYSTEM="gr8" NDATA="IMAGE" name="gr8"></istex:entity><istex:entity SYSTEM="gr9" NDATA="IMAGE" name="gr9"></istex:entity><istex:entity SYSTEM="gr10" NDATA="IMAGE" name="gr10"></istex:entity><istex:entity SYSTEM="gr11" NDATA="IMAGE" name="gr11"></istex:entity><istex:entity SYSTEM="gr12" NDATA="IMAGE" name="gr12"></istex:entity><istex:entity SYSTEM="gr13" NDATA="IMAGE" name="gr13"></istex:entity><istex:entity SYSTEM="gr14" NDATA="IMAGE" name="gr14"></istex:entity><istex:entity SYSTEM="gr15" NDATA="IMAGE" name="gr15"></istex:entity><istex:entity SYSTEM="gr16" NDATA="IMAGE" name="gr16"></istex:entity></istex:docType><istex:document><converted-article version="4.5.2" docsubtype="fla"><item-info><jid>MR</jid><aid>1377</aid><ce:pii>S0026-2714(99)00074-8</ce:pii><ce:doi>10.1016/S0026-2714(99)00074-8</ce:doi><ce:copyright type="full-transfer" year="1999">Elsevier Science Ltd</ce:copyright></item-info><head><ce:title>Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</ce:title><ce:author-group><ce:author><ce:given-name>Heinrich</ce:given-name><ce:surname>Wolf</ce:surname><ce:cross-ref refid="AFF1"><ce:sup>a</ce:sup></ce:cross-ref><ce:cross-ref refid="COR1">*</ce:cross-ref><ce:e-address>wolf@ift.fhg.de</ce:e-address></ce:author><ce:author><ce:given-name>Horst</ce:given-name><ce:surname>Gieser</ce:surname><ce:cross-ref refid="AFF2"><ce:sup>b</ce:sup></ce:cross-ref></ce:author><ce:author><ce:given-name>Wolfgang</ce:given-name><ce:surname>Stadler</ce:surname><ce:cross-ref refid="AFF3"><ce:sup>c</ce:sup></ce:cross-ref></ce:author><ce:affiliation id="AFF1"><ce:label>a</ce:label><ce:textfn>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</ce:textfn></ce:affiliation><ce:affiliation id="AFF2"><ce:label>b</ce:label><ce:textfn>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</ce:textfn></ce:affiliation><ce:affiliation id="AFF3"><ce:label>c</ce:label><ce:textfn>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</ce:textfn></ce:affiliation><ce:correspondence id="COR1"><ce:label>*</ce:label><ce:text>Corresponding author. Tel.: +49-89-54759-031; fax: +49-89-54759-475</ce:text></ce:correspondence></ce:author-group><ce:date-received day="30" month="5" year="1999"></ce:date-received><ce:abstract><ce:section-title>Abstract</ce:section-title><ce:abstract-sec><ce:simple-para>The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain <math altimg="si5.gif">β</math> and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.</ce:simple-para></ce:abstract-sec></ce:abstract><ce:keywords><ce:section-title>Keywords</ce:section-title><ce:keyword><ce:text>ESD</ce:text></ce:keyword><ce:keyword><ce:text>HBM</ce:text></ce:keyword><ce:keyword><ce:text>Compact simulation</ce:text></ce:keyword><ce:keyword><ce:text>Protection structure</ce:text></ce:keyword><ce:keyword><ce:text>Gate coupling</ce:text></ce:keyword><ce:keyword><ce:text>Bipolar transistor model</ce:text></ce:keyword><ce:keyword><ce:text>High current characteristic</ce:text></ce:keyword></ce:keywords></head></converted-article></istex:document></istex:metadataXml><mods version="3.6"><titleInfo><title>Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title></titleInfo><titleInfo type="alternative" contentType="CDATA"><title>Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain</title></titleInfo><name type="personal"><namePart type="given">Heinrich</namePart><namePart type="family">Wolf</namePart><affiliation>E-mail: wolf@ift.fhg.de</affiliation><affiliation>Technische Universität München, Lehrstuhl für Integrierte Schaltungen (TUM/LIS/ATIS Applied Test of Integrated Systems), Arcisstr. 21, D-80290, München, Germany</affiliation><description>Corresponding author. Tel.: +49-89-54759-031; fax: +49-89-54759-475</description><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Horst</namePart><namePart type="family">Gieser</namePart><affiliation>Fraunhofer-Institut Zuverlässigkeit und Mikrointegration (IZM/PCS/ATIS Analysis and Test of Integrated Systems), Hansastr. 27d, D-80686, München, Germany</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Wolfgang</namePart><namePart type="family">Stadler</namePart><affiliation>Infineon Technologies AG, DAT LIB TI, P.O. Box 800949, D-81609, München, Germany</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre type="research-article" displayLabel="Full-length article"></genre><originInfo><publisher>ELSEVIER</publisher><dateIssued encoding="w3cdtf">1999</dateIssued><dateCaptured encoding="w3cdtf">1999-05-30</dateCaptured><copyrightDate encoding="w3cdtf">1999</copyrightDate></originInfo><language><languageTerm type="code" authority="iso639-2b">eng</languageTerm><languageTerm type="code" authority="rfc3066">en</languageTerm></language><physicalDescription><internetMediaType>text/html</internetMediaType></physicalDescription><abstract lang="en">The presented compact model for NMOS transistors combines both the high-current bipolar mode and the MOS mode considering modulation of the current gain β and gate coupling effects. For the studied 0.35 μm-CMOS devices, measurement and simulation correlate very well with respect to layout variations, fulfilling a prerequisite for the simulation guided synthesis and optimization of ESD protection structures and schemes. The open model interface also allows the use of existing proprietary MOS-models.</abstract><note type="content">Fig. 1: The compact bipolar model is attached to a standard MOS model. The gate node influences the trigger behavior of the transistor. The whole structure forms a subcircuit ESD NMOS.</note><note type="content">Fig. 2: Equivalent circuit of the used compact model. The virtual gate node potential influences the avalanche current source Iava.</note><note type="content">Fig. 3: Schematic cross-section of the investigated NMOS protection transistor together with the parasitic bipolar transistor. We investigated several layout variations and compared them to the simulated data.</note><note type="content">Fig. 4: Comparison of the measured high current characteristic of the reference transistor with the simulated data computed with a constant current gain. The differential high current resistance is influenced in the model only by the collector resistor rc. This leads to a deviation of the simulation from the measurement at higher currents.</note><note type="content">Fig. 5: Comparison of the measured multiplication factor with the Miller-formula and a modified Miller function, which is implemented into the transistor model in order to improve the correlation with the measurement at lower device voltages.</note><note type="content">Fig. 6: Measured current gain of the investigated transistor as function of the drain current. For currents higher than 0.2 A, the gain decreases stronger.</note><note type="content">Fig. 7: Simulation of the current dependent gain for different proportionality constants cβ, influencing the decay of β and thus the differential high current resistance of the device. For the simulations we applied a cβ=1.43 A−1.</note><note type="content">Fig. 8: Comparison of the measured high current characteristic of the reference transistor with the simulated data computed with a stress current dependent current gain. The accuracy is significantly increased as compared to Fig. 4.</note><note type="content">Fig. 9: TLP characteristics of three devices with different high currents normalized to their gate width. The decreasing current density with increasing gate width indicates a inhomogenous current distribution.</note><note type="content">Fig. 10: Comparison of TLP measurements with compact simulation with variation of the gate width. The simulation correlates well with the measurement if an inhomogenous current distribution is taken into account.</note><note type="content">Fig. 11: Comparison of TLP measurements with compact simulation with variation of the gate length. The simulation again, correlates well with the measurement.</note><note type="content">Fig. 12: Comparison of TLP measurements with compact simulation with variation of the drain contact/gate spacing aD.</note><note type="content">Fig. 13: Transfer characteristics of the investigated NMOS protection transistor for different drain voltages. The MOS current influences the avalanche current of the parasitic bipolar transistor.</note><note type="content">Fig. 14: IV-characteristic of the bipolar model (without attached MOS model) for several gate voltages Vgs at the virtual gate node.</note><note type="content">Fig. 15: Comparison of the measured DC output characteristic for a gate voltage Vgs=1.5 V in comparison with the simulation. For the simulation, we extended a Berkeley Spice level 1 MOST with the bipolar transistor.</note><note type="content">Fig. 16: Simulation of the drain and gate potential for different coupling capacitances. The trigger voltage does not automatically decrease if a capacitance is introduced between drain and gate. For the simulation we applied a TLP pulse with 5 ns rise time.</note><subject><genre>Keywords</genre><topic>ESD</topic><topic>HBM</topic><topic>Compact simulation</topic><topic>Protection structure</topic><topic>Gate coupling</topic><topic>Bipolar transistor model</topic><topic>High current characteristic</topic></subject><relatedItem type="host"><titleInfo><title>Microelectronics Reliability</title></titleInfo><titleInfo type="abbreviated"><title>MR</title></titleInfo><genre type="Journal">journal</genre><originInfo><dateIssued encoding="w3cdtf">199911</dateIssued></originInfo><identifier type="ISSN">0026-2714</identifier><identifier type="PII">S0026-2714(00)X0052-2</identifier><part><date>199911</date><detail type="volume"><number>39</number><caption>vol.</caption></detail><detail type="issue"><number>11</number><caption>no.</caption></detail><extent unit="issue pages"><start>1519</start><end>1720</end></extent><extent unit="pages"><start>1541</start><end>1549</end></extent></part></relatedItem><identifier type="istex">37DBA566093327825538A3415119203C1D7BC3A3</identifier><identifier type="DOI">10.1016/S0026-2714(99)00074-8</identifier><identifier type="PII">S0026-2714(99)00074-8</identifier><accessCondition type="use and reproduction" contentType="">© 1999Elsevier Science Ltd</accessCondition><recordInfo><recordContentSource>ELSEVIER</recordContentSource><recordOrigin>Elsevier Science Ltd, ©1999</recordOrigin></recordInfo></mods></metadata><enrichments><istex:catWosTEI uri="https://api.istex.fr/document/37DBA566093327825538A3415119203C1D7BC3A3/enrichments/catWos"><teiHeader><profileDesc><textClass><classCode scheme="WOS">ENGINEERING, ELECTRICAL & ELECTRONIC</classCode><classCode scheme="WOS">PHYSICS, APPLIED</classCode><classCode scheme="WOS">NANOSCIENCE & NANOTECHNOLOGY</classCode></textClass></profileDesc></teiHeader></istex:catWosTEI></enrichments><serie></serie></istex></record>Pour manipuler ce document sous Unix (Dilib)
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