A parallel architecture for relaxation operations
Identifieur interne : 003584 ( Istex/Corpus ); précédent : 003583; suivant : 003585A parallel architecture for relaxation operations
Auteurs : Masaru Kamada ; Kazuo Toraichi ; Ryoichi Mori ; Kazuhiko Yamamoto ; Hiromitsu YamadaSource :
- Pattern Recognition [ 0031-3203 ] ; 1987.
Abstract
Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.
Url:
DOI: 10.1016/0031-3203(88)90025-8
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But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.</div></front></TEI><istex><corpusName>elsevier</corpusName><author><json:item><name>Masaru Kamada</name><affiliations><json:string>Doctoral Program in Engineering, University of Tsukuba 1-1 Ten-noudai, Sakura, Niihari, Ibaraki, 305 Japan</json:string></affiliations></json:item><json:item><name>Kazuo Toraichi</name><affiliations><json:string>To whom correspondence should be addressed.</json:string><json:string>Institute of Information Sciences and Electronics, University of Tsukuba 1-1 Ten-noudai, Sakura, Niihari, Ibaraki, 305 Japan</json:string></affiliations></json:item><json:item><name>Ryoichi Mori</name><affiliations><json:string>Institute of Information Sciences and Electronics, University of Tsukuba 1-1 Ten-noudai, Sakura, Niihari, Ibaraki, 305 Japan</json:string></affiliations></json:item><json:item><name>Kazuhiko Yamamoto</name><affiliations><json:string>Electrotechnical Laboratory, MITI, 1-1 Umezono, Sakura, Niihari, Ibaraki, 305 Japan</json:string></affiliations></json:item><json:item><name>Hiromitsu Yamada</name><affiliations><json:string>Electrotechnical Laboratory, MITI, 1-1 Umezono, Sakura, Niihari, Ibaraki, 305 Japan</json:string></affiliations></json:item></author><subject><json:item><lang><json:string>eng</json:string></lang><value>Relaxation method</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Parallel architecture</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Round-robin structure</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Handwritten character recognition</value></json:item><json:item><lang><json:string>eng</json:string></lang><value>Very large scale integration (VLSI)</value></json:item></subject><language><json:string>eng</json:string></language><abstract>Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. 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Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.</p></abstract><textClass><keywords scheme="keyword"><list><head>Keywords</head><item><term>Relaxation method</term></item><item><term>Parallel architecture</term></item><item><term>Round-robin structure</term></item><item><term>Handwritten character recognition</term></item><item><term>Very large scale integration (VLSI)</term></item></list></keywords></textClass></profileDesc><revisionDesc><change when="1987-03-16">Received</change><change when="1987">Published</change></revisionDesc></teiHeader></istex:fulltextTEI></fulltext><metadata><istex:metadataXml wicri:clean="Elsevier, elements deleted: tail"><istex:xmlDeclaration>version="1.0" encoding="utf-8"</istex:xmlDeclaration><istex:docType PUBLIC="-//ES//DTD journal article DTD version 4.5.2//EN//XML" URI="art452.dtd" name="istex:docType"></istex:docType><istex:document><converted-article version="4.5.2" docsubtype="fla"><item-info><jid>PR</jid><aid>88900258</aid><ce:pii>0031-3203(88)90025-8</ce:pii><ce:doi>10.1016/0031-3203(88)90025-8</ce:doi><ce:copyright type="unknown" year="1988"></ce:copyright></item-info><head><ce:title>A parallel architecture for relaxation operations</ce:title><ce:author-group><ce:author><ce:given-name>Masaru</ce:given-name><ce:surname>Kamada</ce:surname><ce:cross-ref refid="AFF1"><ce:sup>∗</ce:sup></ce:cross-ref></ce:author><ce:author><ce:given-name>Kazuo</ce:given-name><ce:surname>Toraichi</ce:surname><ce:cross-ref refid="COR1"><ce:sup>‡</ce:sup></ce:cross-ref><ce:cross-ref refid="AFF2"><ce:sup>†</ce:sup></ce:cross-ref></ce:author><ce:author><ce:given-name>Ryoichi</ce:given-name><ce:surname>Mori</ce:surname><ce:cross-ref refid="AFF2"><ce:sup>†</ce:sup></ce:cross-ref></ce:author><ce:author><ce:given-name>Kazuhiko</ce:given-name><ce:surname>Yamamoto</ce:surname><ce:cross-ref refid="AFF3"><ce:sup>§</ce:sup></ce:cross-ref></ce:author><ce:author><ce:given-name>Hiromitsu</ce:given-name><ce:surname>Yamada</ce:surname><ce:cross-ref refid="AFF3"><ce:sup>§</ce:sup></ce:cross-ref></ce:author><ce:affiliation id="AFF1"><ce:label>∗</ce:label><ce:textfn>Doctoral Program in Engineering, University of Tsukuba 1-1 Ten-noudai, Sakura, Niihari, Ibaraki, 305 Japan</ce:textfn></ce:affiliation><ce:affiliation id="AFF2"><ce:label>†</ce:label><ce:textfn>Institute of Information Sciences and Electronics, University of Tsukuba 1-1 Ten-noudai, Sakura, Niihari, Ibaraki, 305 Japan</ce:textfn></ce:affiliation><ce:affiliation id="AFF3"><ce:label>§</ce:label><ce:textfn>Electrotechnical Laboratory, MITI, 1-1 Umezono, Sakura, Niihari, Ibaraki, 305 Japan</ce:textfn></ce:affiliation><ce:correspondence id="COR1"><ce:label>‡</ce:label><ce:text>To whom correspondence should be addressed.</ce:text></ce:correspondence></ce:author-group><ce:date-received day="16" month="3" year="1987"></ce:date-received><ce:abstract><ce:section-title>Abstract</ce:section-title><ce:abstract-sec><ce:simple-para>Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. 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