Hierarchical array processor system (HAP)
Identifieur interne : 002E52 ( Istex/Corpus ); précédent : 002E51; suivant : 002E53Hierarchical array processor system (HAP)
Auteurs : Shigeharu Momoi ; Shigeo Shimada ; Masamitsu Kobayashi ; Tsutomu IshikawaSource :
- Lecture Notes in Computer Science [ 0302-9743 ] ; 1986.
Abstract
Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.
Url:
DOI: 10.1007/3-540-16811-7_185
Links to Exploration step
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<front><div type="abstract" xml:lang="en">Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</div>
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<ChapterHeader><AuthorGroup><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Shigeharu</GivenName>
<FamilyName>Momoi</FamilyName>
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<Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Shigeo</GivenName>
<FamilyName>Shimada</FamilyName>
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<Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Masamitsu</GivenName>
<FamilyName>Kobayashi</FamilyName>
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<Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Tsutomu</GivenName>
<FamilyName>Ishikawa</FamilyName>
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<Affiliation ID="Aff1"><OrgName>NIT Electrical Communications Laboratories</OrgName>
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<Country>Japan</Country>
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<Abstract ID="Abs1" Language="En"><Heading>Abstract</Heading>
<Para>A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</Para>
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<name type="personal"><namePart type="given">Masamitsu</namePart>
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<name type="personal"><namePart type="given">Tsutomu</namePart>
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<abstract lang="en">Abstract: A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.</abstract>
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