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Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

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Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

Auteurs : C. T Hsu [Australie] ; M. M Lau [Australie] ; Y. T Yeow [Australie]

Source :

Microelectronics Reliability [ 0026-2714 ] ; 2001.

RBID : ISTEX:14FC3D559A1DA6BBE7E6CE201C2372BB773FEECA

Descripteurs français

Wicri :
- topic : Microélectronique, Oxyde, Simulation.

English descriptors

Abstract

Abstract: The use of gate-to-drain capacitance (Cgd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET’s has been reviewed and demonstrated. By analyzing the change in Cgd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (Ibmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Qot, through gate-to-substrate capacitance (Cgb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device’s structure.

Url:

https://api.istex.fr/document/14FC3D559A1DA6BBE7E6CE201C2372BB773FEECA/fulltext/pdf

DOI: 10.1016/S0026-2714(00)00222-5

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Le document en format XML

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<term>Capacitance measurement</term>
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<term>Channel region</term>
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<term>Experimental results</term>
<term>Extraction method</term>
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<term>Gate edge</term>
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<term>Gate oxide</term>
<term>Gate voltage</term>
<term>Hand side</term>
<term>Higher band</term>
<term>Ibmax stress</term>
<term>Ieee</term>
<term>Ieee electron</term>
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<term>Interface charges</term>
<term>Interface states</term>
<term>Interface trap</term>
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<term>Inversion</term>
<term>Inversion layer</term>
<term>Larger portion</term>
<term>Local threshold voltage</term>
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<term>Measurement frequency</term>
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<term>Microelectronics reliability</term>
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<term>Capacitance</term>
<term>Capacitance measurement</term>
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<term>Cryogenic probe station</term>
<term>Cryogenic temperature</term>
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<term>Degradation</term>
<term>Dominant defect type</term>
<term>Donor states</term>
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<term>Drain side</term>
<term>Elsevier science</term>
<term>Experimental results</term>
<term>Extraction method</term>
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<term>Gate edge</term>
<term>Gate electrode</term>
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<term>Gate voltage</term>
<term>Hand side</term>
<term>Higher band</term>
<term>Ibmax stress</term>
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<term>Ieee electron</term>
<term>Ieee trans electron</term>
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<term>Interface traps</term>
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<term>Negative charges</term>
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<term>Positive charge</term>
<term>Positive charges</term>
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<front><div type="abstract" xml:lang="en">Abstract: The use of gate-to-drain capacitance (Cgd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET’s has been reviewed and demonstrated. By analyzing the change in Cgd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (Ibmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Qot, through gate-to-substrate capacitance (Cgb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device’s structure.</div>
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Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

Source :

Descripteurs français

English descriptors

Abstract

Links toward previous steps (curation, corpus...)

Links to Exploration step

Le document en format XML

Pour manipuler ce document sous Unix (Dilib)

Pour mettre un lien sur cette page dans le réseau Wicri