FPNA: interaction between FPGA and neural computation.
Identifieur interne : 000185 ( PubMed/Curation ); précédent : 000184; suivant : 000186FPNA: interaction between FPGA and neural computation.
Auteurs : B. Girau [France]Source :
- International journal of neural systems [ 0129-0657 ] ; 2000.
Descripteurs français
- KwdFr :
- MESH :
English descriptors
- KwdEn :
- MESH :
Abstract
Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed, allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.
DOI: 10.1142/S0129065700000211
PubMed: 11011795
Links toward previous steps (curation, corpus...)
- to stream PubMed, to step Corpus: Pour aller vers cette notice dans l'étape Curation :000185
Links to Exploration step
pubmed:11011795Le document en format XML
<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en">FPNA: interaction between FPGA and neural computation.</title><author><name sortKey="Girau, B" sort="Girau, B" uniqKey="Girau B" first="B" last="Girau">B. Girau</name><affiliation wicri:level="1"><nlm:affiliation>LORIA INRIA-Lorraine, campus scientifique,Vandoeuvre-les-Nancy, France. girau@loria.fr</nlm:affiliation><country xml:lang="fr">France</country><wicri:regionArea>LORIA INRIA-Lorraine, campus scientifique,Vandoeuvre-les-Nancy</wicri:regionArea></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">PubMed</idno><date when="2000">2000</date><idno type="RBID">pubmed:11011795</idno><idno type="pmid">11011795</idno><idno type="doi">10.1142/S0129065700000211</idno><idno type="wicri:Area/PubMed/Corpus">000185</idno><idno type="wicri:explorRef" wicri:stream="PubMed" wicri:step="Corpus" wicri:corpus="PubMed">000185</idno><idno type="wicri:Area/PubMed/Curation">000185</idno><idno type="wicri:explorRef" wicri:stream="PubMed" wicri:step="Curation">000185</idno></publicationStmt><sourceDesc><biblStruct><analytic><title xml:lang="en">FPNA: interaction between FPGA and neural computation.</title><author><name sortKey="Girau, B" sort="Girau, B" uniqKey="Girau B" first="B" last="Girau">B. Girau</name><affiliation wicri:level="1"><nlm:affiliation>LORIA INRIA-Lorraine, campus scientifique,Vandoeuvre-les-Nancy, France. girau@loria.fr</nlm:affiliation><country xml:lang="fr">France</country><wicri:regionArea>LORIA INRIA-Lorraine, campus scientifique,Vandoeuvre-les-Nancy</wicri:regionArea></affiliation></author></analytic><series><title level="j">International journal of neural systems</title><idno type="ISSN">0129-0657</idno><imprint><date when="2000" type="published">2000</date></imprint></series></biblStruct></sourceDesc></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Computers</term><term>Models, Neurological</term><term>Models, Theoretical</term><term>Neural Networks (Computer)</term><term>Signal Processing, Computer-Assisted</term></keywords><keywords scheme="KwdFr" xml:lang="fr"><term>Modèles neurologiques</term><term>Modèles théoriques</term><term>Ordinateurs</term><term>Réseaux neuronaux (ordinateur)</term><term>Traitement du signal assisté par ordinateur</term></keywords><keywords scheme="MESH" xml:lang="en"><term>Computers</term><term>Models, Neurological</term><term>Models, Theoretical</term><term>Neural Networks (Computer)</term><term>Signal Processing, Computer-Assisted</term></keywords><keywords scheme="MESH" xml:lang="fr"><term>Modèles neurologiques</term><term>Modèles théoriques</term><term>Ordinateurs</term><term>Réseaux neuronaux (ordinateur)</term><term>Traitement du signal assisté par ordinateur</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed, allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.</div></front></TEI><pubmed><MedlineCitation Owner="NLM" Status="MEDLINE"><PMID Version="1">11011795</PMID><DateCreated><Year>2001</Year><Month>01</Month><Day>04</Day></DateCreated><DateCompleted><Year>2001</Year><Month>02</Month><Day>08</Day></DateCompleted><Article PubModel="Print"><Journal><ISSN IssnType="Print">0129-0657</ISSN><JournalIssue CitedMedium="Print"><Volume>10</Volume><Issue>3</Issue><PubDate><Year>2000</Year><Month>Jun</Month></PubDate></JournalIssue><Title>International journal of neural systems</Title><ISOAbbreviation>Int J Neural Syst</ISOAbbreviation></Journal><ArticleTitle>FPNA: interaction between FPGA and neural computation.</ArticleTitle><Pagination><MedlinePgn>243-59</MedlinePgn></Pagination><Abstract><AbstractText>Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed, allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.</AbstractText></Abstract><AuthorList CompleteYN="Y"><Author ValidYN="Y"><LastName>Girau</LastName><ForeName>B</ForeName><Initials>B</Initials><AffiliationInfo><Affiliation>LORIA INRIA-Lorraine, campus scientifique,Vandoeuvre-les-Nancy, France. girau@loria.fr</Affiliation></AffiliationInfo></Author></AuthorList><Language>eng</Language><PublicationTypeList><PublicationType UI="D016428">Journal Article</PublicationType></PublicationTypeList></Article><MedlineJournalInfo><Country>SINGAPORE</Country><MedlineTA>Int J Neural Syst</MedlineTA><NlmUniqueID>9100527</NlmUniqueID><ISSNLinking>0129-0657</ISSNLinking></MedlineJournalInfo><CitationSubset>IM</CitationSubset><MeshHeadingList><MeshHeading><DescriptorName MajorTopicYN="Y" UI="D003201">Computers</DescriptorName></MeshHeading><MeshHeading><DescriptorName MajorTopicYN="N" UI="D008959">Models, Neurological</DescriptorName></MeshHeading><MeshHeading><DescriptorName MajorTopicYN="N" UI="D008962">Models, Theoretical</DescriptorName></MeshHeading><MeshHeading><DescriptorName MajorTopicYN="Y" UI="D016571">Neural Networks (Computer)</DescriptorName></MeshHeading><MeshHeading><DescriptorName MajorTopicYN="N" UI="D012815">Signal Processing, Computer-Assisted</DescriptorName></MeshHeading></MeshHeadingList></MedlineCitation><PubmedData><History><PubMedPubDate PubStatus="pubmed"><Year>2000</Year><Month>9</Month><Day>30</Day><Hour>11</Hour><Minute>0</Minute></PubMedPubDate><PubMedPubDate PubStatus="medline"><Year>2001</Year><Month>3</Month><Day>3</Day><Hour>10</Hour><Minute>1</Minute></PubMedPubDate><PubMedPubDate PubStatus="entrez"><Year>2000</Year><Month>9</Month><Day>30</Day><Hour>11</Hour><Minute>0</Minute></PubMedPubDate></History><PublicationStatus>ppublish</PublicationStatus><ArticleIdList><ArticleId IdType="pubmed">11011795</ArticleId><ArticleId IdType="doi">10.1142/S0129065700000211</ArticleId></ArticleIdList></PubmedData></pubmed></record>Pour manipuler ce document sous Unix (Dilib)
EXPLOR_STEP=$WICRI_ROOT/Wicri/Lorraine/explor/InforLorV4/Data/PubMed/Curation
HfdSelect -h $EXPLOR_STEP/biblio.hfd -nk 000185 | SxmlIndent | more
Ou
HfdSelect -h $EXPLOR_AREA/Data/PubMed/Curation/biblio.hfd -nk 000185 | SxmlIndent | more
Pour mettre un lien sur cette page dans le réseau Wicri
{{Explor lien
|wiki= Wicri/Lorraine
|area= InforLorV4
|flux= PubMed
|étape= Curation
|type= RBID
|clé= pubmed:11011795
|texte= FPNA: interaction between FPGA and neural computation.
}}
Pour générer des pages wiki
HfdIndexSelect -h $EXPLOR_AREA/Data/PubMed/Curation/RBID.i -Sk "pubmed:11011795" \
| HfdSelect -Kh $EXPLOR_AREA/Data/PubMed/Curation/biblio.hfd \
| NlmPubMed2Wicri -a InforLorV4
| This area was generated with Dilib version V0.6.33. |  |