Une architecture massivement parallèle intégrée
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Auteurs : Bernard Faure ; S. Mahmoud Karabernou ; Guy Mazaré ; Eric Payan ; Pascal RubiniSource :
- Annales des Télécommunications [ 0003-4347 ] ; 1991-01-01.
English descriptors
- KwdEn :
Abstract
Résumé: Cet article présente une nouvelle architecture MIMD massivement parallèle, intermédiaire entre la Connection Machine et les hypercubes de processeurs 32 bits. Elle est composée de processeurs 8 bits spécifiques connectés en grille bidimensionnelle et communiquant par échanges de messages. Les problèmes de communication, de jeu ďinstructions et de programmation sont étudiés, ainsi que ľusage ďun langage à flots de données de haut niveau.
Abstract: This paper presents a new massively parallel MIMD architecture, halfway between the Connection Machine and hypercubes based on 32-bit processors. It is built from specific 8-bit processors arranged in a 2-D grid and communicating by message transfers. We discuss the communication problems, the instruction set of the basic processing unit, the programmation of the whole array and the use of a high level data-flow language.
Url:
DOI: 10.1007/BF02995439
Affiliations:
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Mahmoud Karabernou</name></author><author><name sortKey="Mazare, Guy" sort="Mazare, Guy" uniqKey="Mazare G" first="Guy" last="Mazaré">Guy Mazaré</name></author><author><name sortKey="Payan, Eric" sort="Payan, Eric" uniqKey="Payan E" first="Eric" last="Payan">Eric Payan</name></author><author><name sortKey="Rubini, Pascal" sort="Rubini, Pascal" uniqKey="Rubini P" first="Pascal" last="Rubini">Pascal Rubini</name></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:A89319E875E9580F1649A5DCC8BEA339E258C564</idno><date when="1991" year="1991">1991</date><idno type="doi">10.1007/BF02995439</idno><idno type="url">https://api.istex.fr/ark:/67375/1BB-P404NZZ0-V/fulltext.pdf</idno><idno type="wicri:Area/Istex/Corpus">002784</idno><idno type="wicri:explorRef" wicri:stream="Istex" wicri:step="Corpus" wicri:corpus="ISTEX">002784</idno><idno type="wicri:Area/Istex/Curation">002751</idno><idno type="wicri:Area/Istex/Checkpoint">003078</idno><idno type="wicri:explorRef" wicri:stream="Istex" wicri:step="Checkpoint">003078</idno><idno type="wicri:doubleKey">0003-4347:1991:Faure B:une:architecture:massivement</idno><idno type="wicri:Area/Main/Merge">00E289</idno><idno type="wicri:Area/Main/Curation">00DA11</idno><idno type="wicri:Area/Main/Exploration">00DA11</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a" type="main" xml:lang="fr">Une architecture massivement parallèle intégrée</title><author><name sortKey="Faure, Bernard" sort="Faure, Bernard" uniqKey="Faure B" first="Bernard" last="Faure">Bernard Faure</name><affiliation><wicri:noCountry code="subField">cedex</wicri:noCountry></affiliation></author><author><name sortKey="Karabernou, S Mahmoud" sort="Karabernou, S Mahmoud" uniqKey="Karabernou S" first="S. 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Télécommun.</title><idno type="ISSN">0003-4347</idno><idno type="eISSN">1958-9395</idno><imprint><publisher>Springer-Verlag</publisher><pubPlace>Paris</pubPlace><date type="published" when="1991-01-01">1991-01-01</date><biblScope unit="volume">46</biblScope><biblScope unit="issue">1-2</biblScope><biblScope unit="page" from="90">90</biblScope><biblScope unit="page" to="100">100</biblScope></imprint><idno type="ISSN">0003-4347</idno></series></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">0003-4347</idno></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Cellular structure</term><term>Computer architecture</term><term>Grid structure</term><term>MIMD computer</term><term>Multiprocessor</term><term>Parallel system</term><term>Programming</term></keywords></textClass><langUsage><language ident="fr">fr</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="fr">Résumé: Cet article présente une nouvelle architecture MIMD massivement parallèle, intermédiaire entre la Connection Machine et les hypercubes de processeurs 32 bits. Elle est composée de processeurs 8 bits spécifiques connectés en grille bidimensionnelle et communiquant par échanges de messages. Les problèmes de communication, de jeu ďinstructions et de programmation sont étudiés, ainsi que ľusage ďun langage à flots de données de haut niveau.</div><div type="abstract" xml:lang="en">Abstract: This paper presents a new massively parallel MIMD architecture, halfway between the Connection Machine and hypercubes based on 32-bit processors. It is built from specific 8-bit processors arranged in a 2-D grid and communicating by message transfers. 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