Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement
Identifieur interne : 003D87 ( Hal/Corpus ); précédent : 003D86; suivant : 003D88Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement
Auteurs : Dominique Cansell ; Camel Tanougast ; Yves Berviller ; Dominique Méry ; Cyril Proch ; Hassan Rabah ; Serge WeberSource :
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Abstract
Designs are usually verified by simulation based on created stimuli; it makes possible to detect some errors in the design process. However, simulation can not find all possible errors in a design. This is why we use a design process based on the B method for specification and refinement of hardware systems. This allows us to obtain an error-free hardware architecture with respect to classical simulation. The goal of this paper is to demonstrate that it is possible to avoid simulations part of a design process.
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However, simulation can not find all possible errors in a design. This is why we use a design process based on the B method for specification and refinement of hardware systems. This allows us to obtain an error-free hardware architecture with respect to classical simulation. The goal of this paper is to demonstrate that it is possible to avoid simulations part of a design process.</div></front></TEI><hal api="V3"><titleStmt><title xml:lang="en">Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement</title><author role="aut"><persName><forename type="first">Dominique</forename><surname>Cansell</surname></persName><email>Dominique.Cansell@loria.fr</email><idno type="halauthor">130116</idno><orgName ref="#struct-364584"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Camel</forename><surname>Tanougast</surname></persName><email></email><idno type="halauthor">131084</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Yves</forename><surname>Berviller</surname></persName><email></email><idno type="halauthor">131085</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Dominique</forename><surname>Méry</surname></persName><email></email><idno type="idhal">dominiquemery</idno><idno type="halauthor">129877</idno><orgName ref="#struct-364475"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Cyril</forename><surname>Proch</surname></persName><email></email><idno type="halauthor">131086</idno><orgName ref="#struct-364475"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Hassan</forename><surname>Rabah</surname></persName><email></email><idno type="halauthor">131087</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Serge</forename><surname>Weber</surname></persName><email></email><idno type="halauthor">131088</idno><orgName ref="#struct-364900"></orgName></author><editor role="depositor"><persName><forename>Publications</forename><surname>Loria</surname></persName><email>publications@loria.fr</email></editor></titleStmt><editionStmt><edition n="v1" type="current"><date type="whenSubmitted">2006-09-26 09:41:37</date><date type="whenModified">2016-05-19 01:09:34</date><date type="whenReleased">2006-09-28 15:22:46</date><date type="whenProduced">2003</date></edition><respStmt><resp>contributor</resp><name key="108626"><persName><forename>Publications</forename><surname>Loria</surname></persName><email>publications@loria.fr</email></name></respStmt></editionStmt><publicationStmt><distributor>CCSD</distributor><idno type="halId">inria-00099834</idno><idno type="halUri">https://hal.inria.fr/inria-00099834</idno><idno type="halBibtex">cansell:inria-00099834</idno><idno type="halRefHtml">Forum on specification and Design Languages - FDL'03, 2003, Frankfurt, Germany, 12 p, 2003</idno><idno type="halRef">Forum on specification and Design Languages - FDL'03, 2003, Frankfurt, Germany, 12 p, 2003</idno></publicationStmt><seriesStmt><idno type="stamp" n="INRIA">INRIA - Institut National de Recherche en Informatique et en Automatique</idno><idno type="stamp" n="CNRS">CNRS - Centre national de la recherche scientifique</idno><idno type="stamp" n="INPL">Institut National Polytechnique de Lorraine</idno><idno type="stamp" n="LORIA2">Publications du LORIA</idno><idno type="stamp" n="INRIA-NANCY-GRAND-EST">INRIA Nancy - Grand Est</idno><idno type="stamp" n="LORIA-FM" p="LORIA">Méthodes formelles</idno><idno type="stamp" n="LORIA">LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications</idno><idno type="stamp" n="UNIV-LORRAINE">Université de Lorraine</idno><idno type="stamp" n="INRIA-LORRAINE">INRIA Nancy - Grand Est</idno><idno type="stamp" n="LABO-LORIA-SET" p="LORIA">LABO-LORIA-SET</idno></seriesStmt><notesStmt><note type="commentary">Colloque avec actes et comité de lecture. internationale.</note><note type="audience" n="2">International</note><note type="invited" n="0">No</note><note type="popular" n="0">No</note><note type="peer" n="1">Yes</note><note type="proceedings" n="1">Yes</note></notesStmt><sourceDesc><biblStruct><analytic><title xml:lang="en">Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement</title><author role="aut"><persName><forename type="first">Dominique</forename><surname>Cansell</surname></persName><email>Dominique.Cansell@loria.fr</email><idno type="halAuthorId">130116</idno><orgName ref="#struct-364584"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Camel</forename><surname>Tanougast</surname></persName><idno type="halAuthorId">131084</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Yves</forename><surname>Berviller</surname></persName><idno type="halAuthorId">131085</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Dominique</forename><surname>Méry</surname></persName><idno type="idHal">dominiquemery</idno><idno type="halAuthorId">129877</idno><orgName ref="#struct-364475"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Cyril</forename><surname>Proch</surname></persName><idno type="halAuthorId">131086</idno><orgName ref="#struct-364475"></orgName><affiliation ref="#struct-2357"></affiliation></author><author role="aut"><persName><forename type="first">Hassan</forename><surname>Rabah</surname></persName><idno type="halAuthorId">131087</idno><orgName ref="#struct-364900"></orgName></author><author role="aut"><persName><forename type="first">Serge</forename><surname>Weber</surname></persName><idno type="halAuthorId">131088</idno><orgName ref="#struct-364900"></orgName></author></analytic><monogr><idno type="localRef">A03-R-129 || cansell03b</idno><meeting><title>Forum on specification and Design Languages - FDL'03</title><date type="start">2003</date><settlement>Frankfurt, Germany</settlement></meeting><imprint><biblScope unit="pp">12 p</biblScope><date type="datePub">2003</date></imprint></monogr></biblStruct></sourceDesc><profileDesc><langUsage><language ident="en">English</language></langUsage><textClass><keywords scheme="author"><term xml:lang="fr">refinement</term><term xml:lang="fr">conception</term><term xml:lang="fr">architecture</term><term xml:lang="fr">raffinement</term></keywords><classCode scheme="halDomain" n="info.info-oh">Computer Science [cs]/Other [cs.OH]</classCode><classCode scheme="halTypology" n="COMM">Conference papers</classCode></textClass><abstract xml:lang="en">Designs are usually verified by simulation based on created stimuli; it makes possible to detect some errors in the design process. However, simulation can not find all possible errors in a design. This is why we use a design process based on the B method for specification and refinement of hardware systems. This allows us to obtain an error-free hardware architecture with respect to classical simulation. The goal of this paper is to demonstrate that it is possible to avoid simulations part of a design process.</abstract></profileDesc></hal></record>Pour manipuler ce document sous Unix (Dilib)
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