Hardware/Software Codesign for Embedded Implementation of Neural Networks
Identifieur interne : 003582 ( Istex/Corpus ); précédent : 003581; suivant : 003583Hardware/Software Codesign for Embedded Implementation of Neural Networks
Auteurs : Cesar Torres-Huitzil ; Bernard Girau ; Adrien GauffriauSource :
- Lecture Notes in Computer Science [ 0302-9743 ]
Abstract
Abstract: The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.
Url:
DOI: 10.1007/978-3-540-71431-6_16
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ISTEX:E16B7E49DBBCB478D15EA4459A371ED76DAA1639Le document en format XML
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This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.</div></front></TEI><istex><corpusName>springer-ebooks</corpusName><author><json:item><name>Cesar Torres-Huitzil</name><affiliations><json:string>Computer Science Department, INAOE, Apdo. Postal 51 and 216, Puebla, Mexico</json:string><json:string>E-mail: ctorres@inaoep.mx</json:string></affiliations></json:item><json:item><name>Bernard Girau</name><affiliations><json:string>CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. P. 239, Vandoeuvre-les-Nancy Cedex, France</json:string><json:string>E-mail: Bernard.Girau@loria.fr</json:string></affiliations></json:item><json:item><name>Adrien Gauffriau</name><affiliations><json:string>CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. 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In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. 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Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.</p></abstract><textClass ana="subject"><keywords scheme="book-subject-collection"><list><label>SUCO11645</label><item><term>Computer Science</term></item></list></keywords></textClass><textClass ana="subject"><keywords scheme="book-subject"><list><label>I</label><item><term type="Primary">Computer Science</term></item><label>I1200X</label><item><term type="Secondary" subtype="priority-1">Computer Hardware</term></item><label>I13014</label><item><term type="Secondary" subtype="priority-2">Processor Architectures</term></item><label>I13022</label><item><term type="Secondary" subtype="priority-3">Computer Communication Networks</term></item><label>I13049</label><item><term type="Secondary" subtype="priority-4">System Performance and Evaluation</term></item><label>I13057</label><item><term type="Secondary" subtype="priority-5">Computer System Implementation</term></item></list></keywords></textClass><langUsage><language ident="EN"></language></langUsage></profileDesc></teiHeader></istex:fulltextTEI><json:item><extension>txt</extension><original>false</original><mimetype>text/plain</mimetype><uri>https://api.istex.fr/ark:/67375/HCB-LQW2X27L-K/fulltext.txt</uri></json:item></fulltext><metadata><istex:metadataXml wicri:clean="corpus springer-ebooks not found" wicri:toSee="no header"><istex:xmlDeclaration>version="1.0" encoding="UTF-8"</istex:xmlDeclaration><istex:docType PUBLIC="-//Springer-Verlag//DTD A++ V2.4//EN" URI="http://devel.springer.de/A++/V2.4/DTD/A++V2.4.dtd" name="istex:docType"></istex:docType><istex:document><Publisher><PublisherInfo><PublisherName>Springer Berlin Heidelberg</PublisherName><PublisherLocation>Berlin, Heidelberg</PublisherLocation></PublisherInfo><Series><SeriesInfo SeriesType="Series" TocLevels="0"><SeriesID>558</SeriesID><SeriesPrintISSN>0302-9743</SeriesPrintISSN><SeriesElectronicISSN>1611-3349</SeriesElectronicISSN><SeriesTitle Language="En">Lecture Notes in Computer Science</SeriesTitle><SeriesAbbreviatedTitle>LNCS</SeriesAbbreviatedTitle></SeriesInfo><SeriesHeader><EditorGroup><Editor><EditorName DisplayOrder="Western"><GivenName>David</GivenName><FamilyName>Hutchison</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Takeo</GivenName><FamilyName>Kanade</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Josef</GivenName><FamilyName>Kittler</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Jon</GivenName><GivenName>M.</GivenName><FamilyName>Kleinberg</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Friedemann</GivenName><FamilyName>Mattern</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>John</GivenName><GivenName>C.</GivenName><FamilyName>Mitchell</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Moni</GivenName><FamilyName>Naor</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Oscar</GivenName><FamilyName>Nierstrasz</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>C.</GivenName><GivenName>Pandu</GivenName><FamilyName>Rangan</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Bernhard</GivenName><FamilyName>Steffen</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Madhu</GivenName><FamilyName>Sudan</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Demetri</GivenName><FamilyName>Terzopoulos</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Doug</GivenName><FamilyName>Tygar</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Moshe</GivenName><GivenName>Y.</GivenName><FamilyName>Vardi</FamilyName></EditorName></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Gerhard</GivenName><FamilyName>Weikum</FamilyName></EditorName></Editor></EditorGroup></SeriesHeader><Book Language="En"><BookInfo BookProductType="Proceedings" ContainsESM="No" Language="En" MediaType="eBook" NumberingStyle="Unnumbered" OutputMedium="All" TocLevels="0"><BookID>978-3-540-71431-6</BookID><BookTitle>Reconfigurable Computing: Architectures, Tools and Applications</BookTitle><BookSubTitle>Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Proceedings</BookSubTitle><BookVolumeNumber>4419</BookVolumeNumber><BookSequenceNumber>4419</BookSequenceNumber><BookDOI>10.1007/978-3-540-71431-6</BookDOI><BookTitleID>148460</BookTitleID><BookPrintISBN>978-3-540-71430-9</BookPrintISBN><BookElectronicISBN>978-3-540-71431-6</BookElectronicISBN><BookChapterCount>38</BookChapterCount><BookCopyright><CopyrightHolderName>Springer-Verlag Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2007</CopyrightYear></BookCopyright><BookSubjectGroup><BookSubject Code="I" Type="Primary">Computer Science</BookSubject><BookSubject Code="I1200X" Priority="1" Type="Secondary">Computer Hardware</BookSubject><BookSubject Code="I13014" Priority="2" Type="Secondary">Processor Architectures</BookSubject><BookSubject Code="I13022" Priority="3" Type="Secondary">Computer Communication Networks</BookSubject><BookSubject Code="I13049" Priority="4" Type="Secondary">System Performance and Evaluation</BookSubject><BookSubject Code="I13057" Priority="5" Type="Secondary">Computer System Implementation</BookSubject><SubjectCollection Code="SUCO11645">Computer Science</SubjectCollection></BookSubjectGroup></BookInfo><BookHeader><EditorGroup><Editor><EditorName DisplayOrder="Western"><GivenName>Pedro</GivenName><GivenName>C.</GivenName><FamilyName>Diniz</FamilyName></EditorName><Contact><Email>pedro.diniz@tagus.istl.utl.pt</Email></Contact></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Eduardo</GivenName><FamilyName>Marques</FamilyName></EditorName><Contact><Email>emarques@icmc.usp.br</Email></Contact></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Koen</GivenName><FamilyName>Bertels</FamilyName></EditorName><Contact><Email>k.l.m.bertels@ewi.tudelft.nl</Email></Contact></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>Marcio</GivenName><GivenName>Merino</GivenName><FamilyName>Fernandes</FamilyName></EditorName><Contact><Email>mmfernan@unimep.br</Email></Contact></Editor><Editor><EditorName DisplayOrder="Western"><GivenName>João</GivenName><GivenName>M.</GivenName><GivenName>P.</GivenName><FamilyName>Cardoso</FamilyName></EditorName><Contact><Email>jmpc@acm.org</Email></Contact></Editor></EditorGroup></BookHeader><Part ID="Part3"><PartInfo TocLevels="0"><PartID>3</PartID><PartSequenceNumber>3</PartSequenceNumber><PartTitle>Mapping Techniques and Tools [Regular Papers]</PartTitle><PartChapterCount>8</PartChapterCount></PartInfo><Chapter ID="Chap16" Language="En"><ChapterInfo ChapterType="OriginalPaper" ContainsESM="No" NumberingStyle="Unnumbered" TocLevels="0"><ChapterID>16</ChapterID><ChapterDOI>10.1007/978-3-540-71431-6_16</ChapterDOI><ChapterSequenceNumber>16</ChapterSequenceNumber><ChapterTitle Language="En">Hardware/Software Codesign for Embedded Implementation of Neural Networks</ChapterTitle><ChapterFirstPage>167</ChapterFirstPage><ChapterLastPage>178</ChapterLastPage><ChapterCopyright><CopyrightHolderName>Springer Berlin Heidelberg</CopyrightHolderName><CopyrightYear>2007</CopyrightYear></ChapterCopyright><ChapterGrants Type="Regular"><MetadataGrant Grant="OpenAccess"></MetadataGrant><AbstractGrant Grant="OpenAccess"></AbstractGrant><BodyPDFGrant Grant="Restricted"></BodyPDFGrant><BodyHTMLGrant Grant="Restricted"></BodyHTMLGrant><BibliographyGrant Grant="Restricted"></BibliographyGrant><ESMGrant Grant="Restricted"></ESMGrant></ChapterGrants></ChapterInfo><ChapterHeader><AuthorGroup><Author AffiliationIDS="Aff1"><AuthorName DisplayOrder="Western"><GivenName>Cesar</GivenName><FamilyName>Torres-Huitzil</FamilyName></AuthorName><Contact><Email>ctorres@inaoep.mx</Email></Contact></Author><Author AffiliationIDS="Aff2"><AuthorName DisplayOrder="Western"><GivenName>Bernard</GivenName><FamilyName>Girau</FamilyName></AuthorName><Contact><Email>Bernard.Girau@loria.fr</Email></Contact></Author><Author AffiliationIDS="Aff2"><AuthorName DisplayOrder="Western"><GivenName>Adrien</GivenName><FamilyName>Gauffriau</FamilyName></AuthorName><Contact><Email>Adrien.Gauffriau@loria.fr</Email></Contact></Author><Affiliation ID="Aff1"><OrgName>Computer Science Department, INAOE, Apdo. Postal 51 and 216, Puebla</OrgName><OrgAddress><Country>Mexico</Country></OrgAddress></Affiliation><Affiliation ID="Aff2"><OrgName>CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. P. 239, Vandoeuvre-les-Nancy Cedex</OrgName><OrgAddress><Country>France</Country></OrgAddress></Affiliation></AuthorGroup><Abstract ID="Abs1" Language="En"><Heading>Abstract</Heading><Para>The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.</Para></Abstract></ChapterHeader><NoBody></NoBody></Chapter></Part></Book></Series></Publisher></istex:document></istex:metadataXml><mods version="3.6"><titleInfo lang="en"><title>Hardware/Software Codesign for Embedded Implementation of Neural Networks</title></titleInfo><titleInfo type="alternative" contentType="CDATA"><title>Hardware/Software Codesign for Embedded Implementation of Neural Networks</title></titleInfo><name type="personal"><namePart type="given">Cesar</namePart><namePart type="family">Torres-Huitzil</namePart><affiliation>Computer Science Department, INAOE, Apdo. Postal 51 and 216, Puebla, Mexico</affiliation><affiliation>E-mail: ctorres@inaoep.mx</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Bernard</namePart><namePart type="family">Girau</namePart><affiliation>CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. P. 239, Vandoeuvre-les-Nancy Cedex, France</affiliation><affiliation>E-mail: Bernard.Girau@loria.fr</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Adrien</namePart><namePart type="family">Gauffriau</namePart><affiliation>CORTEX team, LORIA-INRIA Lorraine Campus Scientifique, B. P. 239, Vandoeuvre-les-Nancy Cedex, France</affiliation><affiliation>E-mail: Adrien.Gauffriau@loria.fr</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre displayLabel="OriginalPaper" authority="ISTEX" authorityURI="https://content-type.data.istex.fr" type="conference" valueURI="https://content-type.data.istex.fr/ark:/67375/XTP-BFHXPBJJ-3">conference</genre><originInfo><publisher>Springer Berlin Heidelberg</publisher><place><placeTerm type="text">Berlin, Heidelberg</placeTerm></place><dateIssued encoding="w3cdtf">2007</dateIssued><copyrightDate encoding="w3cdtf">2007</copyrightDate></originInfo><language><languageTerm type="code" authority="rfc3066">en</languageTerm><languageTerm type="code" authority="iso639-2b">eng</languageTerm></language><abstract lang="en">Abstract: The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.</abstract><relatedItem type="host"><titleInfo><title>Reconfigurable Computing: Architectures, Tools and Applications</title><subTitle>Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. 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