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Embedded harmonic control for dynamic trajectory planning on FPGA

Identifieur interne : 001F28 ( Hal/Corpus ); précédent : 001F27; suivant : 001F29

Embedded harmonic control for dynamic trajectory planning on FPGA

Auteurs : Bernard Girau ; Amine Boumaza

Source :

RBID : Hal:inria-00119491

Abstract

This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated computation of the harmonic functions, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be immediately taken into account, for example when obstacles are discovered during an on-line exploration. The implementation results show that the proposed architecture simultaneously improves speed, power consumption, precision, and environment size.

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Hal:inria-00119491

Le document en format XML

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<div type="abstract" xml:lang="en">This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated computation of the harmonic functions, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be immediately taken into account, for example when obstacles are discovered during an on-line exploration. The implementation results show that the proposed architecture simultaneously improves speed, power consumption, precision, and environment size.</div>
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<idno type="stamp" n="CNRS">CNRS - Centre national de la recherche scientifique</idno>
<idno type="stamp" n="INPL">Institut National Polytechnique de Lorraine</idno>
<idno type="stamp" n="LORIA2">Publications du LORIA</idno>
<idno type="stamp" n="INRIA-NANCY-GRAND-EST">INRIA Nancy - Grand Est</idno>
<idno type="stamp" n="LORIA-CSAI" p="LORIA">Systèmes complexes et intelligence artificielle</idno>
<idno type="stamp" n="LORIA">LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications</idno>
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<idno type="stamp" n="UNIV-LORRAINE">Université de Lorraine</idno>
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<analytic>
<title xml:lang="en">Embedded harmonic control for dynamic trajectory planning on FPGA</title>
<author role="aut">
<persName>
<forename type="first">Bernard</forename>
<surname>Girau</surname>
</persName>
<email>Bernard.Girau@loria.fr</email>
<idno type="halAuthorId">56303</idno>
<affiliation ref="#struct-2348"></affiliation>
</author>
<author role="aut">
<persName>
<forename type="first">Amine</forename>
<surname>Boumaza</surname>
</persName>
<email>amine.boumaza@loria.fr</email>
<idno type="halAuthorId">151546</idno>
<orgName ref="#struct-300292"></orgName>
<affiliation ref="#struct-2355"></affiliation>
</author>
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<meeting>
<title>The IASTED International Conference on Artificial Intelligence and Apllications - AIA 2006</title>
<date type="start">2007-02-12</date>
<settlement>Innsbruck</settlement>
<country key="AU">Australia</country>
</meeting>
<imprint>
<date type="datePub">2007-02-12</date>
</imprint>
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<classCode scheme="halDomain" n="info.info-au">Computer Science [cs]/Automatic Control Engineering</classCode>
<classCode scheme="halTypology" n="COMM">Conference papers</classCode>
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<abstract xml:lang="en">This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated computation of the harmonic functions, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be immediately taken into account, for example when obstacles are discovered during an on-line exploration. The implementation results show that the proposed architecture simultaneously improves speed, power consumption, precision, and environment size.</abstract>
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