Scheduling expression DAGs for minimal register need
Identifieur interne : 001373 ( Istex/Curation ); précédent : 001372; suivant : 001374Scheduling expression DAGs for minimal register need
Auteurs : Christoph W. Kessler1 [Allemagne]Source :
- Computer Languages [ 0096-0551 ] ; 1998.
Abstract
Generating schedules for expression DAGs that use a minimal number of registers is a classical NP-complete optimization problem. Up to now an exact solution could only be computed for small DAGs (with up to 20 nodes), using a trivial O(n!) enumeration algorithm. We present a new algorithm with worst-case complexity O(n22n) and very good average behavior. Applying a dynamic programming scheme and reordering techniques, our algorithm is able to defer the combinatorial explosion and to generate an optimal schedule not only for small DAGs but also for medium-sized ones with up to 50 nodes, a class that contains nearly all DAGs encountered in typical application programs. Experiments with randomly generated DAGs and large DAGs from real application programs confirm that the new algorithm generates optimal schedules quite fast. We extend our algorithm to cope with delay slots and multiple functional units, two common features of modern superscalar processors.
Url:
DOI: 10.1016/S0096-0551(98)00002-2
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<record><TEI wicri:istexFullTextTei="biblStruct"><teiHeader><fileDesc><titleStmt><title>Scheduling expression DAGs for minimal register need</title><author><name sortKey="Kessler1, Christoph W" sort="Kessler1, Christoph W" uniqKey="Kessler1 C" first="Christoph W." last="Kessler1">Christoph W. Kessler1</name><affiliation wicri:level="1"><mods:affiliation>FB 4 — Informatik, Universität Trier, D-54286 Trier, Germany</mods:affiliation><country xml:lang="fr">Allemagne</country><wicri:regionArea>FB 4 — Informatik, Universität Trier, D-54286 Trier</wicri:regionArea></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:05DEE45F06AC2589021C00311CF21F99695D673C</idno><date when="1998" year="1998">1998</date><idno type="doi">10.1016/S0096-0551(98)00002-2</idno><idno type="url">https://api.istex.fr/document/05DEE45F06AC2589021C00311CF21F99695D673C/fulltext/pdf</idno><idno type="wicri:Area/Istex/Corpus">001485</idno><idno type="wicri:explorRef" wicri:stream="Istex" wicri:step="Corpus" wicri:corpus="ISTEX">001485</idno><idno type="wicri:Area/Istex/Curation">001373</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a">Scheduling expression DAGs for minimal register need</title><author><name sortKey="Kessler1, Christoph W" sort="Kessler1, Christoph W" uniqKey="Kessler1 C" first="Christoph W." last="Kessler1">Christoph W. Kessler1</name><affiliation wicri:level="1"><mods:affiliation>FB 4 — Informatik, Universität Trier, D-54286 Trier, Germany</mods:affiliation><country xml:lang="fr">Allemagne</country><wicri:regionArea>FB 4 — Informatik, Universität Trier, D-54286 Trier</wicri:regionArea></affiliation></author></analytic><monogr></monogr><series><title level="j">Computer Languages</title><title level="j" type="abbrev">CL</title><idno type="ISSN">0096-0551</idno><imprint><publisher>ELSEVIER</publisher><date type="published" when="1998">1998</date><biblScope unit="volume">24</biblScope><biblScope unit="issue">1</biblScope><biblScope unit="page" from="33">33</biblScope><biblScope unit="page" to="53">53</biblScope></imprint><idno type="ISSN">0096-0551</idno></series><idno type="istex">05DEE45F06AC2589021C00311CF21F99695D673C</idno><idno type="DOI">10.1016/S0096-0551(98)00002-2</idno><idno type="PII">S0096-0551(98)00002-2</idno></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">0096-0551</idno></seriesStmt></fileDesc><profileDesc><textClass></textClass><langUsage><language ident="en">en</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Generating schedules for expression DAGs that use a minimal number of registers is a classical NP-complete optimization problem. Up to now an exact solution could only be computed for small DAGs (with up to 20 nodes), using a trivial O(n!) enumeration algorithm. We present a new algorithm with worst-case complexity O(n22n) and very good average behavior. Applying a dynamic programming scheme and reordering techniques, our algorithm is able to defer the combinatorial explosion and to generate an optimal schedule not only for small DAGs but also for medium-sized ones with up to 50 nodes, a class that contains nearly all DAGs encountered in typical application programs. Experiments with randomly generated DAGs and large DAGs from real application programs confirm that the new algorithm generates optimal schedules quite fast. We extend our algorithm to cope with delay slots and multiple functional units, two common features of modern superscalar processors.</div></front></TEI></record>Pour manipuler ce document sous Unix (Dilib)
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