Serveur d'exploration sur l'Université de Trèves

Attention, ce site est en cours de développement !
Attention, site généré par des moyens informatiques à partir de corpus bruts.
Les informations ne sont donc pas validées.

Using logic programming and coroutining for electronic CAD

Identifieur interne : 001282 ( Istex/Corpus ); précédent : 001281; suivant : 001283

Using logic programming and coroutining for electronic CAD

Auteurs : Ulrich Bieker ; Andreas Neumann

Source :

RBID : ISTEX:AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F

Abstract

We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.

Url:
DOI: 10.1016/0743-1066(95)00099-2

Links to Exploration step

ISTEX:AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F

Le document en format XML

<record>
<TEI wicri:istexFullTextTei="biblStruct">
<teiHeader>
<fileDesc>
<titleStmt>
<title>Using logic programming and coroutining for electronic CAD</title>
<author>
<name sortKey="Bieker, Ulrich" sort="Bieker, Ulrich" uniqKey="Bieker U" first="Ulrich" last="Bieker">Ulrich Bieker</name>
<affiliation>
<mods:affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</mods:affiliation>
</affiliation>
<affiliation>
<mods:affiliation>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</mods:affiliation>
</affiliation>
</author>
<author>
<name sortKey="Neumann, Andreas" sort="Neumann, Andreas" uniqKey="Neumann A" first="Andreas" last="Neumann">Andreas Neumann</name>
<affiliation>
<mods:affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</mods:affiliation>
</affiliation>
<affiliation>
<mods:affiliation>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</mods:affiliation>
</affiliation>
</author>
</titleStmt>
<publicationStmt>
<idno type="wicri:source">ISTEX</idno>
<idno type="RBID">ISTEX:AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F</idno>
<date when="1996" year="1996">1996</date>
<idno type="doi">10.1016/0743-1066(95)00099-2</idno>
<idno type="url">https://api.istex.fr/document/AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F/fulltext/pdf</idno>
<idno type="wicri:Area/Istex/Corpus">001282</idno>
<idno type="wicri:explorRef" wicri:stream="Istex" wicri:step="Corpus" wicri:corpus="ISTEX">001282</idno>
</publicationStmt>
<sourceDesc>
<biblStruct>
<analytic>
<title level="a">Using logic programming and coroutining for electronic CAD</title>
<author>
<name sortKey="Bieker, Ulrich" sort="Bieker, Ulrich" uniqKey="Bieker U" first="Ulrich" last="Bieker">Ulrich Bieker</name>
<affiliation>
<mods:affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</mods:affiliation>
</affiliation>
<affiliation>
<mods:affiliation>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</mods:affiliation>
</affiliation>
</author>
<author>
<name sortKey="Neumann, Andreas" sort="Neumann, Andreas" uniqKey="Neumann A" first="Andreas" last="Neumann">Andreas Neumann</name>
<affiliation>
<mods:affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</mods:affiliation>
</affiliation>
<affiliation>
<mods:affiliation>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</mods:affiliation>
</affiliation>
</author>
</analytic>
<monogr></monogr>
<series>
<title level="j">The Journal of Logic Programming</title>
<title level="j" type="abbrev">JLP</title>
<idno type="ISSN">0743-1066</idno>
<imprint>
<publisher>ELSEVIER</publisher>
<date type="published" when="1996">1996</date>
<biblScope unit="volume">26</biblScope>
<biblScope unit="issue">2</biblScope>
<biblScope unit="page" from="199">199</biblScope>
<biblScope unit="page" to="215">215</biblScope>
</imprint>
<idno type="ISSN">0743-1066</idno>
</series>
<idno type="istex">AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F</idno>
<idno type="DOI">10.1016/0743-1066(95)00099-2</idno>
<idno type="PII">0743-1066(95)00099-2</idno>
</biblStruct>
</sourceDesc>
<seriesStmt>
<idno type="ISSN">0743-1066</idno>
</seriesStmt>
</fileDesc>
<profileDesc>
<textClass></textClass>
<langUsage>
<language ident="en">en</language>
</langUsage>
</profileDesc>
</teiHeader>
<front>
<div type="abstract" xml:lang="en">We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.</div>
</front>
</TEI>
<istex>
<corpusName>elsevier</corpusName>
<author>
<json:item>
<name>Ulrich Bieker</name>
<affiliations>
<json:string>E-mail: bieker@ls12.informatik.uni-dortmund.de</json:string>
<json:string>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</json:string>
</affiliations>
</json:item>
<json:item>
<name>Andreas Neumann</name>
<affiliations>
<json:string>E-mail: bieker@ls12.informatik.uni-dortmund.de</json:string>
<json:string>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</json:string>
</affiliations>
</json:item>
</author>
<language>
<json:string>eng</json:string>
</language>
<originalGenre>
<json:string>Full-length article</json:string>
</originalGenre>
<abstract>We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.</abstract>
<qualityIndicators>
<score>6.38</score>
<pdfVersion>1.2</pdfVersion>
<pdfPageSize>468 x 699 pts</pdfPageSize>
<refBibsNative>true</refBibsNative>
<keywordCount>0</keywordCount>
<abstractCharCount>822</abstractCharCount>
<pdfWordCount>6539</pdfWordCount>
<pdfCharCount>34831</pdfCharCount>
<pdfPageCount>17</pdfPageCount>
<abstractWordCount>115</abstractWordCount>
</qualityIndicators>
<title>Using logic programming and coroutining for electronic CAD</title>
<pii>
<json:string>0743-1066(95)00099-2</json:string>
</pii>
<refBibs>
<json:item>
<author>
<json:item>
<name>C Albrecht</name>
</json:item>
<json:item>
<name>S Bashford</name>
</json:item>
<json:item>
<name>P Marwedel</name>
</json:item>
<json:item>
<name>A Neumann</name>
</json:item>
<json:item>
<name>W Schenk</name>
</json:item>
</author>
<host>
<pages>
<last>259</last>
<first>254</first>
</pages>
<author></author>
<title>4th EUROCHIP Workshop on VLSI Training</title>
</host>
<title>The Design of the PRIPS Microprocessor</title>
</json:item>
<json:item>
<author>
<json:item>
<name>S Bashford</name>
</json:item>
<json:item>
<name>U Bieker</name>
</json:item>
<json:item>
<name>B Harking</name>
</json:item>
<json:item>
<name>R Leupers</name>
</json:item>
<json:item>
<name>P Marwedel</name>
</json:item>
<json:item>
<name>A Neumann</name>
</json:item>
<json:item>
<name>D Voggenauer</name>
</json:item>
</author>
<host>
<author></author>
<title>Technical Report</title>
</host>
<title>The MIMOLA Language-Version 4.1</title>
</json:item>
<json:item>
<host>
<author></author>
<title>Constraint Logic Programming: Selected Research</title>
</host>
</json:item>
<json:item>
<host>
<author></author>
</host>
</json:item>
<json:item>
<author>
<json:item>
<name>U Bieker</name>
</json:item>
</author>
<host>
<author></author>
<title>Version 4.0</title>
</host>
<serie>
<author></author>
<title>Version 4.0</title>
</serie>
<title>On the Semantics of the TREEMOLA Language</title>
</json:item>
<json:item>
<author>
<json:item>
<name>R Beckmann</name>
</json:item>
<json:item>
<name>W Schenk</name>
</json:item>
<json:item>
<name>D Pusch</name>
</json:item>
<json:item>
<name>R Joehnk</name>
</json:item>
</author>
<host>
<author></author>
<title>Version 4.0</title>
</host>
<serie>
<author></author>
<title>Version 4.0</title>
</serie>
<title>The TREEMOLA Language Reference Manual</title>
</json:item>
<json:item>
<author>
<json:item>
<name>W.F Clocksin</name>
</json:item>
</author>
<host>
<volume>4</volume>
<pages>
<last>82</last>
<first>59</first>
</pages>
<author></author>
<title>J. Logic Programming</title>
</host>
<title>Logic Programming and Digital Circuit Analysis</title>
</json:item>
<json:item>
<author>
<json:item>
<name>G Cheng</name>
</json:item>
<json:item>
<name>C Tsui</name>
</json:item>
<json:item>
<name>I Pyo</name>
</json:item>
<json:item>
<name>I Huang</name>
</json:item>
<json:item>
<name>Y Koh</name>
</json:item>
<json:item>
<name>C Su</name>
</json:item>
<json:item>
<name>S Liu</name>
</json:item>
<json:item>
<name>K Pan</name>
</json:item>
<json:item>
<name>S Wu</name>
</json:item>
<json:item>
<name>H Chen</name>
</json:item>
<json:item>
<name>A Despain</name>
</json:item>
</author>
<host>
<author></author>
<title>First International Conference on the Practical Applications of Prolog</title>
</host>
<title>A Full-Range Design Automation System for Instruction Set Processors</title>
</json:item>
<json:item>
<author>
<json:item>
<name>M Dincbas</name>
</json:item>
<json:item>
<name>H Simonis</name>
</json:item>
<json:item>
<name>P Van Hentenryck</name>
</json:item>
</author>
<host>
<volume>8</volume>
<pages>
<last>93</last>
<first>75</first>
</pages>
<author></author>
<title>J. Logic Programming</title>
</host>
<title>Solving Large Combinatorial Problems in Logic Programming</title>
</json:item>
<json:item>
<host>
<author></author>
<title>ECLIPSE 3.4 User Manual</title>
</host>
</json:item>
<json:item>
<author>
<json:item>
<name>E Gullichsen</name>
</json:item>
</author>
<host>
<volume>3</volume>
<pages>
<last>318</last>
<first>283</first>
</pages>
<author></author>
<title>Integration, VLSI J.</title>
</host>
<title>Heuristic Circuit Simulation Using PROLOG</title>
</json:item>
<json:item>
<author>
<json:item>
<name>P.W Horstmann</name>
</json:item>
</author>
<host>
<author></author>
<title>Dissertation</title>
</host>
<serie>
<author></author>
<title>Dissertation</title>
</serie>
<title>Automation of the Design for Testability Using Logic Programming</title>
</json:item>
<json:item>
<author>
<json:item>
<name>I Huang</name>
</json:item>
<json:item>
<name>A.M Despain</name>
</json:item>
</author>
<host>
<author></author>
<title>29th Design Automation Conference</title>
</host>
<title>High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers</title>
</json:item>
<json:item>
<host>
<author></author>
<title>Design Automation Standards Subcommittee of the IEEE</title>
</host>
</json:item>
<json:item>
<host>
<author></author>
<title>Instruction Set Extraction from Programmable Structures</title>
</host>
</json:item>
<json:item>
<author>
<json:item>
<name>Y Lichtenstein</name>
</json:item>
<json:item>
<name>B Welham</name>
</json:item>
<json:item>
<name>A Gupta</name>
</json:item>
</author>
<host>
<pages>
<last>93</last>
<first>78</first>
</pages>
<author></author>
<title>3rd Annual Conference on Logic Programming</title>
</host>
<title>Time Representation in Prolog Circuit Modelling</title>
</json:item>
<json:item>
<host>
<author></author>
<title>Computer System Architecture</title>
</host>
</json:item>
<json:item>
<author>
<json:item>
<name>P Marwedel</name>
</json:item>
</author>
<host>
<pages>
<last>593</last>
<first>587</first>
</pages>
<author></author>
<title>Proc. 21st Design Automation Conference</title>
</host>
<title>The MIMOLA Design System: Tools for the Design of Digital Processors</title>
</json:item>
<json:item>
<author>
<json:item>
<name>P Marwedel</name>
</json:item>
</author>
<host>
<author></author>
<title>Proc. EDAC 1990</title>
</host>
<title>Matching System and Component Behavior in MIMOLA Synthesis Tools</title>
</json:item>
<json:item>
<author>
<json:item>
<name>M.D Neill</name>
</json:item>
<json:item>
<name>D.D Jani</name>
</json:item>
<json:item>
<name>C.H Cho</name>
</json:item>
<json:item>
<name>J.R Armstrong</name>
</json:item>
</author>
<host>
<pages>
<last>360</last>
<first>347</first>
</pages>
<author></author>
<title>Proceedings of the IFIP WG 10.2 Ninth Int. Symposium on Computer Hardware Description Languages and their Applications</title>
</host>
<title>BTG: A Behavioral Test Generator, Computer Hardware Description Languages and their Applications</title>
</json:item>
<json:item>
<author>
<json:item>
<name>L Nowak</name>
</json:item>
<json:item>
<name>P Marwedel</name>
</json:item>
</author>
<host>
<pages>
<last>447</last>
<first>441</first>
</pages>
<author></author>
<title>26th Design Automation Conference</title>
</host>
<title>Verification of Hardware Descriptions by Retargetable Code Generation</title>
</json:item>
<json:item>
<author>
<json:item>
<name>L Nowak</name>
</json:item>
</author>
<host>
<pages>
<last>132</last>
<first>126</first>
</pages>
<author></author>
<title>20th Annual Workshop on Microprogramming (Micro-20)</title>
</host>
<title>Graph Based Retargetable Microcode Compilation in the MIMOLA Design System</title>
</json:item>
<json:item>
<author>
<json:item>
<name>P.B Reintjes</name>
</json:item>
</author>
<host>
<pages>
<last>562</last>
<first>549</first>
</pages>
<author></author>
<title>Logic Programming, Proc. of the Eight Int. Conference</title>
</host>
<title>A Set of Tools for VHDL Design</title>
</json:item>
<json:item>
<author>
<json:item>
<name>H Simonis</name>
</json:item>
</author>
<host>
<pages>
<last>112</last>
<first>101</first>
</pages>
<author></author>
<title>Proceedings of the 6th International Conference on Logic Programming</title>
</host>
<title>Test Generation Using the Constraint Logic Programming Language CHIP</title>
</json:item>
<json:item>
<author>
<json:item>
<name>H Simonis</name>
</json:item>
<json:item>
<name>N Nguyen</name>
</json:item>
<json:item>
<name>M Dincbas</name>
</json:item>
</author>
<host>
<pages>
<last>442</last>
<first>421</first>
</pages>
<author></author>
<title>The Fusion of Hardware Design and Verification</title>
</host>
<title>Verification of Digital Circuits Using CHIP</title>
</json:item>
<json:item>
<author>
<json:item>
<name>D Svanaes</name>
</json:item>
<json:item>
<name>E.J Aas</name>
</json:item>
</author>
<host>
<volume>2</volume>
<pages>
<last>67</last>
<first>49</first>
</pages>
<author></author>
<title>Integration, VLSI J.</title>
</host>
<title>Test Generation through Logic Programming</title>
</json:item>
<json:item>
<author>
<json:item>
<name>U Bieker</name>
</json:item>
<json:item>
<name>P Marwedel</name>
</json:item>
</author>
<host>
<pages>
<last>611</last>
<first>605</first>
</pages>
<author></author>
<title>Proc. 32nd Design Automation Conference</title>
</host>
<title>Retargetable Self-Test Program Generation Using Constraint Logic Programming</title>
</json:item>
</refBibs>
<genre>
<json:string>research-article</json:string>
</genre>
<serie>
<language>
<json:string>unknown</json:string>
</language>
<title>Version 4.0</title>
</serie>
<host>
<volume>26</volume>
<pii>
<json:string>S0743-1066(00)X0005-2</json:string>
</pii>
<pages>
<last>215</last>
<first>199</first>
</pages>
<issn>
<json:string>0743-1066</json:string>
</issn>
<issue>2</issue>
<genre>
<json:string>journal</json:string>
</genre>
<language>
<json:string>unknown</json:string>
</language>
<title>The Journal of Logic Programming</title>
<publicationDate>1996</publicationDate>
</host>
<publicationDate>1996</publicationDate>
<copyrightDate>1996</copyrightDate>
<doi>
<json:string>10.1016/0743-1066(95)00099-2</json:string>
</doi>
<id>AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F</id>
<score>1.0205235</score>
<fulltext>
<json:item>
<extension>pdf</extension>
<original>true</original>
<mimetype>application/pdf</mimetype>
<uri>https://api.istex.fr/document/AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F/fulltext/pdf</uri>
</json:item>
<json:item>
<extension>zip</extension>
<original>false</original>
<mimetype>application/zip</mimetype>
<uri>https://api.istex.fr/document/AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F/fulltext/zip</uri>
</json:item>
<istex:fulltextTEI uri="https://api.istex.fr/document/AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F/fulltext/tei">
<teiHeader>
<fileDesc>
<titleStmt>
<title level="a">Using logic programming and coroutining for electronic CAD</title>
</titleStmt>
<publicationStmt>
<authority>ISTEX</authority>
<publisher>ELSEVIER</publisher>
<availability>
<p>ELSEVIER</p>
</availability>
<date>1996</date>
</publicationStmt>
<sourceDesc>
<biblStruct type="inbook">
<analytic>
<title level="a">Using logic programming and coroutining for electronic CAD</title>
<author xml:id="author-1">
<persName>
<forename type="first">Ulrich</forename>
<surname>Bieker</surname>
</persName>
<email>bieker@ls12.informatik.uni-dortmund.de</email>
<affiliation>Address correspondence to Ulrich Bieker</affiliation>
<affiliation>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</affiliation>
</author>
<author xml:id="author-2">
<persName>
<forename type="first">Andreas</forename>
<surname>Neumann</surname>
</persName>
<email>bieker@ls12.informatik.uni-dortmund.de</email>
<affiliation>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</affiliation>
</author>
</analytic>
<monogr>
<title level="j">The Journal of Logic Programming</title>
<title level="j" type="abbrev">JLP</title>
<idno type="pISSN">0743-1066</idno>
<idno type="PII">S0743-1066(00)X0005-2</idno>
<imprint>
<publisher>ELSEVIER</publisher>
<date type="published" when="1996"></date>
<biblScope unit="volume">26</biblScope>
<biblScope unit="issue">2</biblScope>
<biblScope unit="page" from="199">199</biblScope>
<biblScope unit="page" to="215">215</biblScope>
</imprint>
</monogr>
<idno type="istex">AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F</idno>
<idno type="DOI">10.1016/0743-1066(95)00099-2</idno>
<idno type="PII">0743-1066(95)00099-2</idno>
</biblStruct>
</sourceDesc>
</fileDesc>
<profileDesc>
<creation>
<date>1996</date>
</creation>
<langUsage>
<language ident="en">en</language>
</langUsage>
<abstract xml:lang="en">
<p>We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.</p>
</abstract>
</profileDesc>
<revisionDesc>
<change when="1996">Published</change>
</revisionDesc>
</teiHeader>
</istex:fulltextTEI>
<json:item>
<extension>txt</extension>
<original>false</original>
<mimetype>text/plain</mimetype>
<uri>https://api.istex.fr/document/AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F/fulltext/txt</uri>
</json:item>
</fulltext>
<metadata>
<istex:metadataXml wicri:clean="Elsevier, elements deleted: tail">
<istex:xmlDeclaration>version="1.0" encoding="utf-8"</istex:xmlDeclaration>
<istex:docType PUBLIC="-//ES//DTD journal article DTD version 4.5.2//EN//XML" URI="art452.dtd" name="istex:docType"></istex:docType>
<istex:document>
<converted-article version="4.5.2" docsubtype="fla">
<item-info>
<jid>JLP</jid>
<aid>95000992</aid>
<ce:pii>0743-1066(95)00099-2</ce:pii>
<ce:doi>10.1016/0743-1066(95)00099-2</ce:doi>
<ce:copyright type="unknown" year="1996"></ce:copyright>
</item-info>
<head>
<ce:title>Using logic programming and coroutining for electronic CAD</ce:title>
<ce:author-group>
<ce:author>
<ce:given-name>Ulrich</ce:given-name>
<ce:surname>Bieker</ce:surname>
<ce:cross-ref refid="COR1">
<ce:sup></ce:sup>
</ce:cross-ref>
<ce:cross-ref refid="AFF1">
<ce:sup>a</ce:sup>
</ce:cross-ref>
<ce:e-address>bieker@ls12.informatik.uni-dortmund.de</ce:e-address>
</ce:author>
<ce:author>
<ce:given-name>Andreas</ce:given-name>
<ce:surname>Neumann</ce:surname>
<ce:cross-ref refid="AFF2">
<ce:sup>b</ce:sup>
</ce:cross-ref>
<ce:e-address>neumann@ti.uni-trier.de</ce:e-address>
</ce:author>
<ce:affiliation id="AFF1">
<ce:label>a</ce:label>
<ce:textfn>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</ce:textfn>
</ce:affiliation>
<ce:affiliation id="AFF2">
<ce:label>b</ce:label>
<ce:textfn>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</ce:textfn>
</ce:affiliation>
<ce:correspondence id="COR1">
<ce:label></ce:label>
<ce:text>Address correspondence to Ulrich Bieker</ce:text>
</ce:correspondence>
</ce:author-group>
<ce:abstract>
<ce:section-title>Abstract</ce:section-title>
<ce:abstract-sec>
<ce:simple-para>We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.</ce:simple-para>
</ce:abstract-sec>
</ce:abstract>
</head>
</converted-article>
</istex:document>
</istex:metadataXml>
<mods version="3.6">
<titleInfo>
<title>Using logic programming and coroutining for electronic CAD</title>
</titleInfo>
<titleInfo type="alternative" contentType="CDATA">
<title>Using logic programming and coroutining for electronic CAD</title>
</titleInfo>
<name type="personal">
<namePart type="given">Ulrich</namePart>
<namePart type="family">Bieker</namePart>
<affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</affiliation>
<affiliation>University of Dortmund, Department of Computer Science, D-44221 Dortmund, Germany</affiliation>
<description>Address correspondence to Ulrich Bieker</description>
<role>
<roleTerm type="text">author</roleTerm>
</role>
</name>
<name type="personal">
<namePart type="given">Andreas</namePart>
<namePart type="family">Neumann</namePart>
<affiliation>E-mail: bieker@ls12.informatik.uni-dortmund.de</affiliation>
<affiliation>Andreas Neumann, University of Trier, Department of Computer Science, D-54286 Trier, Germany</affiliation>
<role>
<roleTerm type="text">author</roleTerm>
</role>
</name>
<typeOfResource>text</typeOfResource>
<genre type="research-article" displayLabel="Full-length article"></genre>
<originInfo>
<publisher>ELSEVIER</publisher>
<dateIssued encoding="w3cdtf">1996</dateIssued>
<copyrightDate encoding="w3cdtf">1996</copyrightDate>
</originInfo>
<language>
<languageTerm type="code" authority="iso639-2b">eng</languageTerm>
<languageTerm type="code" authority="rfc3066">en</languageTerm>
</language>
<physicalDescription>
<internetMediaType>text/html</internetMediaType>
</physicalDescription>
<abstract lang="en">We show how an extended Prolog can be exploited to implement different electronic CAD tools. Starting with a computer hardware description language (CHDL) several problems like digital circuit analysis, simulation, test generation, and code generation for programmable microprocessors are discussed. For that purpose the MIMOLA (machine independent microprogramming language) system MSS (MIMOLA hardware design system) is presented. It is shown that logic programming techniques have several advantages especially in the area of integrated circuit design. One of the main advantages is the small code size, which translates to easy maintenance. We make extensive use of two main features of standard Prolog and constraint logic programming, i.e., backtracking and the coroutining mechanism, to express Boolean constraints.</abstract>
<relatedItem type="host">
<titleInfo>
<title>The Journal of Logic Programming</title>
</titleInfo>
<titleInfo type="abbreviated">
<title>JLP</title>
</titleInfo>
<genre type="journal">journal</genre>
<originInfo>
<dateIssued encoding="w3cdtf">199602</dateIssued>
</originInfo>
<identifier type="ISSN">0743-1066</identifier>
<identifier type="PII">S0743-1066(00)X0005-2</identifier>
<part>
<date>199602</date>
<detail type="volume">
<number>26</number>
<caption>vol.</caption>
</detail>
<detail type="issue">
<number>2</number>
<caption>no.</caption>
</detail>
<extent unit="issue pages">
<start>91</start>
<end>233</end>
</extent>
<extent unit="pages">
<start>199</start>
<end>215</end>
</extent>
</part>
</relatedItem>
<identifier type="istex">AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F</identifier>
<identifier type="DOI">10.1016/0743-1066(95)00099-2</identifier>
<identifier type="PII">0743-1066(95)00099-2</identifier>
<recordInfo>
<recordContentSource>ELSEVIER</recordContentSource>
</recordInfo>
</mods>
</metadata>
</istex>
</record>

Pour manipuler ce document sous Unix (Dilib)

EXPLOR_STEP=$WICRI_ROOT/Wicri/Rhénanie/explor/UnivTrevesV1/Data/Istex/Corpus
HfdSelect -h $EXPLOR_STEP/biblio.hfd -nk 001282 | SxmlIndent | more

Ou

HfdSelect -h $EXPLOR_AREA/Data/Istex/Corpus/biblio.hfd -nk 001282 | SxmlIndent | more

Pour mettre un lien sur cette page dans le réseau Wicri

{{Explor lien
   |wiki=    Wicri/Rhénanie
   |area=    UnivTrevesV1
   |flux=    Istex
   |étape=   Corpus
   |type=    RBID
   |clé=     ISTEX:AC2E95CFD0DA02C250FB0147BE7247153B3B9F7F
   |texte=   Using logic programming and coroutining for electronic CAD
}}

Wicri

This area was generated with Dilib version V0.6.31.
Data generation: Sat Jul 22 16:29:01 2017. Site generation: Wed Feb 28 14:55:37 2024