AustralieFrV1, Istex, Corpus, bibRecord, 000372

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Identifieur interne : 000372 ( Istex/Corpus ); précédent : 000371; suivant : 000373

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Auteurs : D. Munday ; A. Parker ; F. Anghinolfi ; P. Aspell ; M. Campbell ; P. Jarron ; E. H. M. Heijne ; G. Meddeler ; J. C. Santiard ; H. Verweij ; C. Gössling ; R. Bonino ; A. G. Clark ; C. Couyoumtzelis ; D. La Marra ; X. Wu ; G. Moorhead ; A. Weidberg ; D. Campbell ; P. Murray ; P. Seller ; R. Stevens ; E. Beuville ; M. Rouger ; J. Teiger

Source :

Nuclear Inst. and Methods in Physics Research, A [ 0168-9002 ] ; 1993.

RBID : ISTEX:13422D74E98125739D0DEB8BCD629BBA45A742A9

English descriptors

Abstract

Abstract: An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.

Url:

https://api.istex.fr/document/13422D74E98125739D0DEB8BCD629BBA45A742A9/fulltext/pdf

DOI: 10.1016/0168-9002(93)90339-J

Links to Exploration step

ISTEX:13422D74E98125739D0DEB8BCD629BBA45A742A9

Le document en format XML

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<sourceDesc><biblStruct><analytic><title level="a">A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors</title>
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<author><name sortKey="Anghinolfi, F" sort="Anghinolfi, F" uniqKey="Anghinolfi F" first="F." last="Anghinolfi">F. Anghinolfi</name>
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<author><name sortKey="Jarron, P" sort="Jarron, P" uniqKey="Jarron P" first="P." last="Jarron">P. Jarron</name>
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</affiliation>
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<author><name sortKey="Heijne, E H M" sort="Heijne, E H M" uniqKey="Heijne E" first="E. H. M." last="Heijne">E. H. M. Heijne</name>
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<author><name sortKey="Meddeler, G" sort="Meddeler, G" uniqKey="Meddeler G" first="G." last="Meddeler">G. Meddeler</name>
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<author><name sortKey="Gossling, C" sort="Gossling, C" uniqKey="Gossling C" first="C." last="Gössling">C. Gössling</name>
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<author><name sortKey="Bonino, R" sort="Bonino, R" uniqKey="Bonino R" first="R." last="Bonino">R. Bonino</name>
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</affiliation>
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<author><name sortKey="Clark, A G" sort="Clark, A G" uniqKey="Clark A" first="A. G." last="Clark">A. G. Clark</name>
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<author><name sortKey="Couyoumtzelis, C" sort="Couyoumtzelis, C" uniqKey="Couyoumtzelis C" first="C." last="Couyoumtzelis">C. Couyoumtzelis</name>
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</affiliation>
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<author><name sortKey="La Marra, D" sort="La Marra, D" uniqKey="La Marra D" first="D." last="La Marra">D. La Marra</name>
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</affiliation>
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<author><name sortKey="Wu, X" sort="Wu, X" uniqKey="Wu X" first="X." last="Wu">X. Wu</name>
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</affiliation>
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<author><name sortKey="Moorhead, G" sort="Moorhead, G" uniqKey="Moorhead G" first="G." last="Moorhead">G. Moorhead</name>
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</affiliation>
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<author><name sortKey="Weidberg, A" sort="Weidberg, A" uniqKey="Weidberg A" first="A." last="Weidberg">A. Weidberg</name>
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<author><name sortKey="Murray, P" sort="Murray, P" uniqKey="Murray P" first="P." last="Murray">P. Murray</name>
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</affiliation>
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<author><name sortKey="Seller, P" sort="Seller, P" uniqKey="Seller P" first="P." last="Seller">P. Seller</name>
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</affiliation>
</author>
<author><name sortKey="Stevens, R" sort="Stevens, R" uniqKey="Stevens R" first="R." last="Stevens">R. Stevens</name>
<affiliation><mods:affiliation>Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX, UK</mods:affiliation>
</affiliation>
</author>
<author><name sortKey="Beuville, E" sort="Beuville, E" uniqKey="Beuville E" first="E." last="Beuville">E. Beuville</name>
<affiliation><mods:affiliation>Centre d'Etudes Nucléaires de Saclay, F-91191 Gif-sur-Yvette, France</mods:affiliation>
</affiliation>
</author>
<author><name sortKey="Rouger, M" sort="Rouger, M" uniqKey="Rouger M" first="M." last="Rouger">M. Rouger</name>
<affiliation><mods:affiliation>Centre d'Etudes Nucléaires de Saclay, F-91191 Gif-sur-Yvette, France</mods:affiliation>
</affiliation>
</author>
<author><name sortKey="Teiger, J" sort="Teiger, J" uniqKey="Teiger J" first="J." last="Teiger">J. Teiger</name>
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<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Analog</term>
<term>Analog array</term>
<term>Analog information</term>
<term>Analog memories</term>
<term>Analog memory</term>
<term>Analog memory array</term>
<term>Analog memory chip</term>
<term>Analog memory circuit</term>
<term>Anghinolfi</term>
<term>Block diagram</term>
<term>Capacitor</term>
<term>Cern report cern</term>
<term>Clock feedthrough</term>
<term>Clock period</term>
<term>Como conf</term>
<term>Controller cells</term>
<term>Controller diagram</term>
<term>Data processing</term>
<term>Data selection</term>
<term>Dead time</term>
<term>Detector</term>
<term>Dynamic range</term>
<term>Electrical measurements</term>
<term>Energy deposition spectrum</term>
<term>Hadron collider environment</term>
<term>Harp</term>
<term>Harp architecture</term>
<term>Heijne</term>
<term>Icon preamplifier</term>
<term>Ieee nucl science symp conf</term>
<term>Input charge</term>
<term>Jarron</term>
<term>Large number</term>
<term>Latency period</term>
<term>Linearity</term>
<term>Lvli</term>
<term>Maximum latency time</term>
<term>Maximum number</term>
<term>Memory array</term>
<term>Memory cells</term>
<term>Minimum number</term>
<term>More detail</term>
<term>Nucl phys</term>
<term>Output signal</term>
<term>Pedestal</term>
<term>Pedestal nonuniformity</term>
<term>Pedestal variation</term>
<term>Pedestal variations</term>
<term>Power consumption</term>
<term>Power dissipation</term>
<term>Preamplifier</term>
<term>Previous event</term>
<term>Prototype version</term>
<term>Radioactive source</term>
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<term>Readout</term>
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<term>Sensor element</term>
<term>Sensor elements</term>
<term>Signal charge</term>
<term>Silicon</term>
<term>Silicon detector</term>
<term>Sitp</term>
<term>Sitp detector</term>
<term>Storage capacitor</term>
<term>Successive time slices</term>
<term>Time slots</term>
<term>Timing diagram</term>
<term>Transmission gates</term>
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<term>Detector</term>
<term>Dynamic range</term>
<term>Electrical measurements</term>
<term>Energy deposition spectrum</term>
<term>Hadron collider environment</term>
<term>Harp</term>
<term>Harp architecture</term>
<term>Heijne</term>
<term>Icon preamplifier</term>
<term>Ieee nucl science symp conf</term>
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<term>Jarron</term>
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<term>Linearity</term>
<term>Lvli</term>
<term>Maximum latency time</term>
<term>Maximum number</term>
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<term>Memory cells</term>
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<term>Nucl phys</term>
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<term>Pedestal nonuniformity</term>
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<term>Pedestal variations</term>
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<term>Sensor element</term>
<term>Sensor elements</term>
<term>Signal charge</term>
<term>Silicon</term>
<term>Silicon detector</term>
<term>Sitp</term>
<term>Sitp detector</term>
<term>Storage capacitor</term>
<term>Successive time slices</term>
<term>Time slots</term>
<term>Timing diagram</term>
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<term>Voltage swing</term>
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<front><div type="abstract" xml:lang="en">Abstract: An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.</div>
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<ce:author><ce:given-name>C.</ce:given-name>
<ce:surname>Couyoumtzelis</ce:surname>
</ce:author>
<ce:author><ce:given-name>D.</ce:given-name>
<ce:surname>La Marra</ce:surname>
</ce:author>
<ce:author><ce:given-name>X.</ce:given-name>
<ce:surname>Wu</ce:surname>
</ce:author>
<ce:affiliation><ce:textfn>DPNC, Geneva University, CH-1211 Geneva 4, Switzerland</ce:textfn>
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<ce:author-group><ce:author><ce:given-name>G.</ce:given-name>
<ce:surname>Moorhead</ce:surname>
</ce:author>
<ce:affiliation><ce:textfn>School of Physics, University of Melbourne, Parkville, Victoria 3052, Australia</ce:textfn>
</ce:affiliation>
</ce:author-group>
<ce:author-group><ce:author><ce:given-name>A.</ce:given-name>
<ce:surname>Weidberg</ce:surname>
</ce:author>
<ce:affiliation><ce:textfn>Department of Nuclear Physics, Oxford University, Oxford, UK</ce:textfn>
</ce:affiliation>
</ce:author-group>
<ce:author-group><ce:author><ce:given-name>D.</ce:given-name>
<ce:surname>Campbell</ce:surname>
</ce:author>
<ce:author><ce:given-name>P.</ce:given-name>
<ce:surname>Murray</ce:surname>
</ce:author>
<ce:author><ce:given-name>P.</ce:given-name>
<ce:surname>Seller</ce:surname>
</ce:author>
<ce:author><ce:given-name>R.</ce:given-name>
<ce:surname>Stevens</ce:surname>
</ce:author>
<ce:affiliation><ce:textfn>Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX, UK</ce:textfn>
</ce:affiliation>
</ce:author-group>
<ce:author-group><ce:author><ce:given-name>E.</ce:given-name>
<ce:surname>Beuville</ce:surname>
</ce:author>
<ce:author><ce:given-name>M.</ce:given-name>
<ce:surname>Rouger</ce:surname>
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<ce:author><ce:given-name>J.</ce:given-name>
<ce:surname>Teiger</ce:surname>
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<ce:affiliation><ce:textfn>Centre d'Etudes Nucléaires de Saclay, F-91191 Gif-sur-Yvette, France</ce:textfn>
</ce:affiliation>
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<ce:abstract><ce:section-title>Abstract</ce:section-title>
<ce:abstract-sec><ce:simple-para>An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.</ce:simple-para>
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<abstract lang="en">Abstract: An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.</abstract>
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A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

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