Constrained software synthesis for embedded applications
Identifieur interne : 001960 ( Istex/Corpus ); précédent : 001959; suivant : 001961Constrained software synthesis for embedded applications
Auteurs : Rajesh K. Gupta ; Giovanni DemicheliSource :
- Journal of Systems Architecture [ 1383-7621 ] ; 1996.
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- KwdEn :
Abstract
Embedded systems are composed of interacting hardware components such as general-purpose processors and application-specific circuits and software components that execute on the general-purpose hardware. The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. Experimental results show that the proposed algorithm is substantially faster than conventional methods and yields efficient schedules for the embedded software.
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DOI: 10.1016/S1383-7621(96)00125-7
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ISTEX:C95C006E54DCD39467FFDCA1C46EE6D38013EBDELe document en format XML
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Gupta</name><affiliation><mods:affiliation>Information and Computer Science, University of California, Irvine, CA 92697, USA</mods:affiliation></affiliation><affiliation><mods:affiliation>Corresponding author.</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: rgupta@ics.uci.edu</mods:affiliation></affiliation></author><author><name sortKey="Demicheli, Giovanni" sort="Demicheli, Giovanni" uniqKey="Demicheli G" first="Giovanni" last="Demicheli">Giovanni Demicheli</name><affiliation><mods:affiliation>Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA</mods:affiliation></affiliation></author></titleStmt><publicationStmt><idno type="wicri:source">ISTEX</idno><idno type="RBID">ISTEX:C95C006E54DCD39467FFDCA1C46EE6D38013EBDE</idno><date when="1997" year="1997">1997</date><idno type="doi">10.1016/S1383-7621(96)00125-7</idno><idno type="url">https://api.istex.fr/document/C95C006E54DCD39467FFDCA1C46EE6D38013EBDE/fulltext/pdf</idno><idno type="wicri:Area/Istex/Corpus">001960</idno></publicationStmt><sourceDesc><biblStruct><analytic><title level="a" type="main" xml:lang="en">Constrained software synthesis for embedded applications</title><author><name sortKey="Gupta, Rajesh K" sort="Gupta, Rajesh K" uniqKey="Gupta R" first="Rajesh K." last="Gupta">Rajesh K. Gupta</name><affiliation><mods:affiliation>Information and Computer Science, University of California, Irvine, CA 92697, USA</mods:affiliation></affiliation><affiliation><mods:affiliation>Corresponding author.</mods:affiliation></affiliation><affiliation><mods:affiliation>E-mail: rgupta@ics.uci.edu</mods:affiliation></affiliation></author><author><name sortKey="Demicheli, Giovanni" sort="Demicheli, Giovanni" uniqKey="Demicheli G" first="Giovanni" last="Demicheli">Giovanni Demicheli</name><affiliation><mods:affiliation>Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA</mods:affiliation></affiliation></author></analytic><monogr></monogr><series><title level="j">Journal of Systems Architecture</title><title level="j" type="abbrev">SYSARC</title><idno type="ISSN">1383-7621</idno><imprint><publisher>ELSEVIER</publisher><date type="published" when="1996">1996</date><biblScope unit="volume">43</biblScope><biblScope unit="issue">8</biblScope><biblScope unit="page" from="557">557</biblScope><biblScope unit="page" to="586">586</biblScope></imprint><idno type="ISSN">1383-7621</idno></series><idno type="istex">C95C006E54DCD39467FFDCA1C46EE6D38013EBDE</idno><idno type="DOI">10.1016/S1383-7621(96)00125-7</idno><idno type="PII">S1383-7621(96)00125-7</idno><idno type="ArticleID">96001257</idno></biblStruct></sourceDesc><seriesStmt><idno type="ISSN">1383-7621</idno></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Embedded software</term><term>Multithreaded software</term><term>Operation linearization</term><term>Operation serializability</term><term>Software synthesis</term></keywords></textClass><langUsage><language ident="en">en</language></langUsage></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Embedded systems are composed of interacting hardware components such as general-purpose processors and application-specific circuits and software components that execute on the general-purpose hardware. The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. Experimental results show that the proposed algorithm is substantially faster than conventional methods and yields efficient schedules for the embedded software.</div></front></TEI><istex><corpusName>elsevier</corpusName><author><json:item><name>Rajesh K. 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The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. 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The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. 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All rights reserved</ce:copyright></item-info><head><ce:title>Constrained software synthesis for embedded applications</ce:title><ce:author-group><ce:author><ce:given-name>Rajesh K.</ce:given-name><ce:surname>Gupta</ce:surname><ce:cross-ref refid="aff1"><ce:sup>a</ce:sup></ce:cross-ref><ce:cross-ref refid="cor1"><ce:sup>*</ce:sup></ce:cross-ref><ce:e-address type="email">rgupta@ics.uci.edu</ce:e-address></ce:author><ce:author><ce:given-name>Giovanni</ce:given-name><ce:surname>DeMicheli</ce:surname><ce:cross-ref refid="aff2"><ce:sup>b</ce:sup></ce:cross-ref></ce:author><ce:affiliation id="aff1"><ce:label>a</ce:label><ce:textfn>Information and Computer Science, University of California, Irvine, CA 92697, USA</ce:textfn></ce:affiliation><ce:affiliation id="aff2"><ce:label>b</ce:label><ce:textfn>Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA</ce:textfn></ce:affiliation><ce:correspondence id="cor1"><ce:label>*</ce:label><ce:text>Corresponding author.</ce:text></ce:correspondence></ce:author-group><ce:date-received day="1" month="7" year="1996"></ce:date-received><ce:date-revised day="2" month="10" year="1996"></ce:date-revised><ce:date-accepted day="7" month="11" year="1996"></ce:date-accepted><ce:abstract id="ab1" class="author" xml:lang="en"><ce:section-title>Abstract</ce:section-title><ce:abstract-sec><ce:simple-para>Embedded systems are composed of interacting hardware components such as general-purpose processors and application-specific circuits and software components that execute on the general-purpose hardware. The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. Experimental results show that the proposed algorithm is substantially faster than conventional methods and yields efficient schedules for the embedded software.</ce:simple-para></ce:abstract-sec></ce:abstract><ce:keywords class="keyword" xml:lang="en"><ce:section-title>Keywords</ce:section-title><ce:keyword><ce:text>Software synthesis</ce:text></ce:keyword><ce:keyword><ce:text>Embedded software</ce:text></ce:keyword><ce:keyword><ce:text>Multithreaded software</ce:text></ce:keyword><ce:keyword><ce:text>Operation linearization</ce:text></ce:keyword><ce:keyword><ce:text>Operation serializability</ce:text></ce:keyword></ce:keywords></head><tail><ce:bibliography><ce:section-title>References</ce:section-title><ce:bibliography-sec><ce:bib-reference id="bib1"><ce:label>[1]</ce:label><sb:reference><sb:contribution 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1995</sb:date><sb:publisher><sb:name>University of Illinois</sb:name></sb:publisher></sb:book></sb:host></sb:reference></ce:bib-reference></ce:bibliography-sec></ce:bibliography></tail></article></istex:document></istex:metadataXml><mods version="3.6"><titleInfo lang="en"><title>Constrained software synthesis for embedded applications</title></titleInfo><titleInfo type="alternative" lang="en" contentType="CDATA"><title>Constrained software synthesis for embedded applications</title></titleInfo><name type="personal"><namePart type="given">Rajesh K.</namePart><namePart type="family">Gupta</namePart><affiliation>Information and Computer Science, University of California, Irvine, CA 92697, USA</affiliation><affiliation>Corresponding author.</affiliation><affiliation>E-mail: rgupta@ics.uci.edu</affiliation><role><roleTerm type="text">author</roleTerm></role></name><name type="personal"><namePart type="given">Giovanni</namePart><namePart type="family">DeMicheli</namePart><affiliation>Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA</affiliation><role><roleTerm type="text">author</roleTerm></role></name><typeOfResource>text</typeOfResource><genre type="research-article" displayLabel="Full-length article"></genre><originInfo><publisher>ELSEVIER</publisher><dateIssued encoding="w3cdtf">1996</dateIssued><dateValid encoding="w3cdtf">1996-11-07</dateValid><dateModified encoding="w3cdtf">1996-10-02</dateModified><copyrightDate encoding="w3cdtf">1997</copyrightDate></originInfo><language><languageTerm type="code" authority="iso639-2b">eng</languageTerm><languageTerm type="code" authority="rfc3066">en</languageTerm></language><physicalDescription><internetMediaType>text/html</internetMediaType></physicalDescription><abstract lang="en">Embedded systems are composed of interacting hardware components such as general-purpose processors and application-specific circuits and software components that execute on the general-purpose hardware. The software component consists of application-specific routines that must deliver the required system functionality under constraints on timing and memory storage available. In this paper, we consider two main problems in the synthesis of the software component in embedded system designs: (a) generation of software and (b) conditions to ensure correct behavior of the generated software from an HDL-modeled input. Generation of embedded software requires operation linearization under constraints to ensure timely interaction with concurrent hardware. We describe our procedure to achieve constrained software generation and the utility of our approach by examples. Experimental results show that the proposed algorithm is substantially faster than conventional methods and yields efficient schedules for the embedded software.</abstract><subject lang="en"><genre>Keywords</genre><topic>Software synthesis</topic><topic>Embedded software</topic><topic>Multithreaded software</topic><topic>Operation linearization</topic><topic>Operation serializability</topic></subject><relatedItem type="host"><titleInfo><title>Journal of Systems Architecture</title></titleInfo><titleInfo type="abbreviated"><title>SYSARC</title></titleInfo><genre type="Journal">journal</genre><originInfo><dateIssued encoding="w3cdtf">199705</dateIssued></originInfo><identifier type="ISSN">1383-7621</identifier><identifier type="PII">S1383-7621(00)X0081-1</identifier><part><date>199705</date><detail type="volume"><number>43</number><caption>vol.</caption></detail><detail type="issue"><number>8</number><caption>no.</caption></detail><extent unit="issue pages"><start>519</start><end>599</end></extent><extent unit="pages"><start>557</start><end>586</end></extent></part></relatedItem><identifier type="istex">C95C006E54DCD39467FFDCA1C46EE6D38013EBDE</identifier><identifier type="DOI">10.1016/S1383-7621(96)00125-7</identifier><identifier type="PII">S1383-7621(96)00125-7</identifier><identifier type="ArticleID">96001257</identifier><accessCondition type="use and reproduction" contentType="">© 1997Elsevier Science B.V. All rights reserved</accessCondition><recordInfo><recordContentSource>ELSEVIER</recordContentSource><recordOrigin>Elsevier Science B.V. All rights reserved, ©1997</recordOrigin></recordInfo></mods></metadata><enrichments><istex:catWosTEI uri="https://api.istex.fr/document/C95C006E54DCD39467FFDCA1C46EE6D38013EBDE/enrichments/catWos"><teiHeader><profileDesc><textClass><classCode scheme="WOS">COMPUTER SCIENCE, HARDWARE & ARCHITECTURE</classCode><classCode scheme="WOS">COMPUTER SCIENCE, SOFTWARE ENGINEERING</classCode></textClass></profileDesc></teiHeader></istex:catWosTEI></enrichments></istex></record>Pour manipuler ce document sous Unix (Dilib)
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