A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System
Identifieur interne : 000752 ( Pmc/Corpus ); précédent : 000751; suivant : 000753A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System
Auteurs : Seung Bae Lee ; Byunghun Lee ; Benoit Gosselin ; Maysam GhovanlooSource :
- Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference [ 1557-170X ] ; 2014.
Abstract
This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm2 and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µVrms in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW.
Url:
DOI: 10.1109/EMBC.2014.6944287
PubMed: 25570655
PubMed Central: 4445086
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PMC:4445086Le document en format XML
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<author><name sortKey="Gosselin, Benoit" sort="Gosselin, Benoit" uniqKey="Gosselin B" first="Benoit" last="Gosselin">Benoit Gosselin</name>
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<front><div type="abstract" xml:lang="en"><p id="P1">This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm<sup>2</sup>
and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µV<sub>rms</sub>
in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW.</p>
</div>
</front>
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<front><journal-meta><journal-id journal-id-type="nlm-journal-id">101243413</journal-id>
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<journal-id journal-id-type="iso-abbrev">Conf Proc IEEE Eng Med Biol Soc</journal-id>
<journal-title-group><journal-title>Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference</journal-title>
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<title-group><article-title>A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System</article-title>
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<contrib-group><contrib contrib-type="author"><name><surname>Lee</surname>
<given-names>Seung Bae</given-names>
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<aff id="A1">GT-Bionics lab, School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA 30308, USA</aff>
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<contrib contrib-type="author"><name><surname>Lee</surname>
<given-names>Byunghun</given-names>
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<aff id="A2">GT-Bionics lab, School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA 30308, USA</aff>
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<contrib contrib-type="author"><name><surname>Gosselin</surname>
<given-names>Benoit</given-names>
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<aff id="A3">Department of Electrical and Computer Engineering, Laval University, Quebec, QC, Canada</aff>
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<contrib contrib-type="author" corresp="yes"><name><surname>Ghovanloo</surname>
<given-names>Maysam</given-names>
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<email>mgh@gatech.edu</email>
<aff id="A4">GT-Bionics lab, School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA 30308, USA</aff>
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<pub-date pub-type="nihms-submitted"><day>20</day>
<month>5</month>
<year>2015</year>
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<pub-date pub-type="ppub"><year>2014</year>
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<pub-date pub-type="pmc-release"><day>27</day>
<month>5</month>
<year>2015</year>
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<volume>2014</volume>
<fpage>3134</fpage>
<lpage>3137</lpage>
<pmc-comment>elocation-id from pubmed: 10.1109/EMBC.2014.6944287</pmc-comment>
<permissions><copyright-statement>Copyright (c) 2014 IEEE</copyright-statement>
<copyright-year>2014</copyright-year>
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<abstract><p id="P1">This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-µm CMOS process, occupying 2.4 × 2.1 mm<sup>2</sup>
and consuming 255 µW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 µV<sub>rms</sub>
in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 µW.</p>
</abstract>
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